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| User's Manual V850/SF1 32-Bit Single-Chip Microcontroller Hardware PD703075AY PD703075AY(A) PD703076AY PD703076AY(A) PD703078AY PD703078AY(A) PD703078Y PD703079AY PD703079AY(A) PD703079Y Document No. U14665EJ4V0UD00 (4th edition) Date Published September 2003 N CP(K) 2000, 2003 Printed in Japan PD70F3079AY PD70F3079AY(A) PD70F3079Y [MEMO] 2 User's Manual U14665EJ4V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. User's Manual U14665EJ4V0UD 3 Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of September, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U14665EJ4V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 User's Manual U14665EJ4V0UD 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850/SF1 and design application systems using the V850/SF1. The target devices are shown below. * Standard products: PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y * Special products: PD703075AY(A), 703076AY(A), 703078AY(A), 703079AY(A), 70F3079AY(A) Purpose This manual is intended to give users an understanding of the hardware functions described in the Organization below. Organization The V850/SF1 User's Manual is divided into two parts: hardware (this manual) and architecture (V850 Series Architecture User's Manual). Hardware * * * * * * Architecture * * * * * Pin functions CPU function Internal peripheral functions Flash memory programming FCAN controller Electrical specifications Data types Register set Instruction format and instruction set Interrupts and exceptions Pipeline operation How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Cautions 1. The application examples in this manual apply to "standard" quality grade products for general electronic systems. When using an example in this manual for an application that requires a "special" quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. When using this manual as a manual for a special grade product, read the part numbers as follows. PD703075AY PD703076AY PD703078AY PD703079AY PD70F3079AY PD703075AY(A) PD703076AY(A) PD703078AY(A) PD703079AY(A) PD70F3079AY(A) 6 User's Manual U14665EJ4V0UD To find out the details of a register whose name is known: Refer to APPENDIX B REGISTER INDEX. To understand the details of an instruction function: Refer to V850 Series Architecture User's Manual available separately. How to read register formats: Names of bits whose numbers are enclosed in a square are defined in the device file under reserved words. To understand the overall functions of the V850/SF1: Read this manual in the order of the CONTENTS. To know the electrical specifications of the V850/SF1: Refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. The mark Conventions shows major revised points. Higher digits on the left and lower digits on the right Data significance: Active low representation: xxx (overscore over pin or signal name) Memory map addresses: Higher addresses at the top and lower addresses at the bottom Note: Caution: Remark: Footnote for items marked with Note in the text Information requiring particular attention Supplementary information Decimal ... xxxx Hexadecimal ... xxxxH Prefixes indicating power of 2 (address space, memory capacity): K (kilo) : 210 = 1024 M (mega) : 220 = 10242 G (giga) : 230 = 10243 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850/SF1 Document Name V850 Series Architecture User's Manual V850/SF1 Hardware User's Manual V850/SF1 FCAN Driver Library Application Note Document No. U10243E This manual U15500E Numerical representation: Binary ... xxxx or xxxxB User's Manual U14665EJ4V0UD 7 Documents related to development tools (user's manuals) Document Name IE-703002-MC (In-Circuit Emulator) IE-703079-MC-EM1 (In-Circuit Emulator Option Board) CA850 Ver. 2.50 C Compiler Package Operation C Language Assembly Language PM plus Ver. 5.10 ID850 Ver. 2.50 Integrated Debugger SM850 Ver.2.50 System Simulator SM850 Ver. 2.00 or Later System Simulator RX850 Ver. 3.13 or Later Real-Time OS Operation Operation External Part User Open Interface Specifications Basics Installation Technical RX850 Pro Ver. 3.15 Real-Time OS Basics Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger AZ850 Ver.3.0 System Performance Analyzer PG-FP3 Flash Memory Programmer PG-FP4 Flash Memory Programmer Document No. U11595E U15447E U16053E U16054E U16042E U16569E U16217E U15182E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E 8 User's Manual U14665EJ4V0UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................17 1.1 1.2 1.3 1.4 1.5 1.6 General ......................................................................................................................................17 Features.....................................................................................................................................18 Applications ..............................................................................................................................19 Ordering Information ...............................................................................................................20 Pin Configuration (Top View) ..................................................................................................21 Function Blocks .......................................................................................................................24 1.6.1 1.6.2 Internal block diagram ................................................................................................................. 24 Internal units................................................................................................................................ 25 CHAPTER 2 PIN FUNCTIONS................................................................................................................28 2.1 2.2 2.3 2.4 2.5 List of Pin Functions................................................................................................................28 Pin States ..................................................................................................................................35 Description of Pin Functions ..................................................................................................36 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins .............44 Pin I/O Circuits..........................................................................................................................46 CHAPTER 3 CPU FUNCTIONS ..............................................................................................................47 3.1 3.2 Features.....................................................................................................................................47 CPU Register Set......................................................................................................................48 3.2.1 3.2.2 Program register set.................................................................................................................... 49 System register set ..................................................................................................................... 50 3.3 3.4 Operation Modes ......................................................................................................................53 Address Space .........................................................................................................................54 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 CPU address space .................................................................................................................... 54 Images ........................................................................................................................................ 55 Wraparound of CPU address space............................................................................................ 56 Memory map ............................................................................................................................... 57 Area ............................................................................................................................................ 58 External expansion mode............................................................................................................ 64 Recommended use of address space ......................................................................................... 65 Peripheral I/O registers ............................................................................................................... 67 Specific registers......................................................................................................................... 74 CHAPTER 4 CLOCK GENERATION FUNCTION .................................................................................76 4.1 4.2 4.3 4.4 General ......................................................................................................................................76 Configuration ............................................................................................................................77 Clock Output Function.............................................................................................................77 4.3.1 4.4.1 4.4.2 4.4.3 Control registers.......................................................................................................................... 78 General ....................................................................................................................................... 82 HALT mode ................................................................................................................................. 83 IDLE mode .................................................................................................................................. 86 User's Manual U14665EJ4V0UD Power Save Functions .............................................................................................................82 9 4.4.4 Software STOP mode..................................................................................................................88 4.5 4.6 Oscillation Stabilization Time..................................................................................................90 Cautions on Power Save Function .........................................................................................91 CHAPTER 5 PORT FUNCTION...............................................................................................................94 5.1 5.2 Port Configuration ....................................................................................................................94 Port Pin Functions....................................................................................................................94 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 Port 0...........................................................................................................................................94 Port 1...........................................................................................................................................98 Port 2.........................................................................................................................................102 Port 3.........................................................................................................................................105 Ports 4 and 5 .............................................................................................................................108 Port 6.........................................................................................................................................111 Ports 7 and 8 .............................................................................................................................113 Port 9.........................................................................................................................................115 Port 10.......................................................................................................................................118 Port 11.......................................................................................................................................121 5.3 5.4 Setting When Port Pin Is Used for Alternate Function ...................................................... 125 Operation of Port Function................................................................................................... 129 5.4.1 5.4.2 Writing data to I/O port ..............................................................................................................129 Reading data from I/O port ........................................................................................................129 CHAPTER 6 BUS CONTROL FUNCTION .......................................................................................... 130 6.1 6.2 6.3 Features.................................................................................................................................. 130 Bus Control Pins and Control Register............................................................................... 130 6.2.1 6.3.1 6.3.2 Bus control pins .........................................................................................................................130 Number of access clocks...........................................................................................................131 Bus width...................................................................................................................................132 Bus Access ............................................................................................................................ 131 6.4 6.5 Memory Block Function........................................................................................................ 133 Wait Function ......................................................................................................................... 134 6.5.1 6.5.2 6.5.3 Programmable wait function ......................................................................................................134 External wait function ................................................................................................................135 Relationship between programmable wait and external wait .....................................................135 6.6 6.7 Idle State Insertion Function ................................................................................................ 136 Bus Hold Function................................................................................................................. 137 6.7.1 6.7.2 6.7.3 Outline of function......................................................................................................................137 Bus hold procedure ...................................................................................................................138 Operation in power save mode..................................................................................................138 6.8 Bus Timing ............................................................................................................................. 139 6.9 Bus Priority ............................................................................................................................ 146 6.10 Memory Boundary Operation Condition ............................................................................. 146 6.10.1 6.10.2 Program space ..........................................................................................................................146 Data space ................................................................................................................................146 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................. 147 7.1 10 Outline .................................................................................................................................... 147 User's Manual U14665EJ4V0UD 7.1.1 Features .................................................................................................................................... 147 Operation .................................................................................................................................. 151 Restore...................................................................................................................................... 153 NP flag ...................................................................................................................................... 154 Noise elimination of NMI pin...................................................................................................... 154 Edge detection function of NMI pin ........................................................................................... 155 Operation .................................................................................................................................. 156 Restore...................................................................................................................................... 158 Priorities of maskable interrupts ................................................................................................ 159 Interrupt control register (xxICn)................................................................................................ 162 In-service priority register (ISPR) .............................................................................................. 165 ID flag........................................................................................................................................ 166 Watchdog timer mode register (WDTM).................................................................................... 167 Noise elimination ....................................................................................................................... 167 Edge detection function............................................................................................................. 169 Operation .................................................................................................................................. 170 Restore...................................................................................................................................... 171 EP flag ...................................................................................................................................... 172 Illegal opcode definition............................................................................................................. 172 Operation .................................................................................................................................. 173 Restore...................................................................................................................................... 174 Priorities of interrupts and exceptions ....................................................................................... 175 Multiple interrupt servicing......................................................................................................... 175 7.2 Non-Maskable Interrupt .........................................................................................................150 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 Maskable Interrupts ...............................................................................................................156 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.4 Software Exception ................................................................................................................170 7.4.1 7.4.2 7.4.3 7.5 Exception Trap .......................................................................................................................172 7.5.1 7.5.2 7.5.3 7.6 Priority Control .......................................................................................................................175 7.6.1 7.6.2 7.7 7.8 Response Time .......................................................................................................................178 Periods in Which Interrupts Are Not Acknowledged..........................................................178 7.8.1 Interrupt request valid timing following EI instruction................................................................. 179 7.9 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer..................180 7.10 Key Interrupt Function...........................................................................................................181 CHAPTER 8 TIMER/COUNTER FUNCTION ........................................................................................183 8.1 16-Bit Timers TM0, TM1, TM7 ................................................................................................183 8.1.1 8.1.2 8.1.3 8.1.4 Outline....................................................................................................................................... 183 Function .................................................................................................................................... 183 Configuration............................................................................................................................. 185 Timer 0, 1, 7 control registers.................................................................................................... 188 Operation as interval timer ........................................................................................................ 197 PPG output operation................................................................................................................ 199 Pulse width measurement ......................................................................................................... 201 Operation as external event counter ......................................................................................... 208 Operation as square-wave output ............................................................................................. 209 Operation as one-shot pulse output .......................................................................................... 211 Cautions .................................................................................................................................... 216 User's Manual U14665EJ4V0UD 8.2 Operation of 16-Bit Timers TM0, TM1, TM7 .........................................................................197 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 11 8.3 16-Bit Timers TM2 to TM6 ..................................................................................................... 221 8.3.1 8.3.2 8.3.3 Functions...................................................................................................................................221 Configuration .............................................................................................................................222 Timer n control register..............................................................................................................223 Operation as interval timer ........................................................................................................228 Operation as external event counter..........................................................................................230 Operation as square-wave output..............................................................................................231 Operation as 16-bit PWM output ...............................................................................................232 Cautions ....................................................................................................................................234 8.4 16-Bit Timer (TM2 to TM6) Operation .................................................................................. 228 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 CHAPTER 9 WATCH TIMER FUNCTION........................................................................................... 235 9.1 9.2 9.3 9.4 Function.................................................................................................................................. 235 Configuration ......................................................................................................................... 236 Watch Timer Control Register.............................................................................................. 237 Operation................................................................................................................................ 239 9.4.1 9.4.2 9.4.3 Operation as watch timer...........................................................................................................239 Operation as interval timer ........................................................................................................239 Cautions ....................................................................................................................................240 CHAPTER 10 WATCHDOG TIMER FUNCTION ................................................................................ 241 10.1 10.2 10.3 10.4 Functions................................................................................................................................ 241 Configuration ......................................................................................................................... 243 Watchdog Timer Control Register ....................................................................................... 243 Operation................................................................................................................................ 246 10.4.1 10.4.2 Operation as watchdog timer.....................................................................................................246 Operation as interval timer ........................................................................................................247 10.5 Standby Function Control Register ..................................................................................... 248 CHAPTER 11 SERIAL INTERFACE FUNCTION ............................................................................... 249 11.1 Overview................................................................................................................................. 249 11.2 3-Wire Serial I/O (CSI0, CSI1, CSI3)...................................................................................... 249 11.2.1 11.2.2 11.2.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 Configuration .............................................................................................................................250 CSIn control registers ................................................................................................................250 Operations.................................................................................................................................252 Configuration .............................................................................................................................258 I2C control registers ...................................................................................................................260 I2C bus mode functions..............................................................................................................271 I2C bus definitions and control methods.....................................................................................272 I2C interrupt request (INTIIC0) ...................................................................................................279 Interrupt request (INTIIC0) generation timing and wait control ..................................................297 Address match detection method ..............................................................................................298 Error detection...........................................................................................................................298 Extension code ..........................................................................................................................298 11.3 I2C Bus .................................................................................................................................... 255 11.3.10 Arbitration ..................................................................................................................................299 11.3.11 Wakeup function........................................................................................................................300 12 User's Manual U14665EJ4V0UD 11.3.12 Communication reservation....................................................................................................... 301 11.3.13 Cautions .................................................................................................................................... 304 11.3.14 Communication operations........................................................................................................ 305 11.3.15 Timing of data communication .................................................................................................. 307 11.4 Asynchronous Serial Interface (UART0, UART1)................................................................314 11.4.1 11.4.2 11.4.3 11.4.4 11.5.1 11.5.2 11.5.3 Configuration............................................................................................................................. 314 UARTn control registers ............................................................................................................ 316 Operations................................................................................................................................. 321 Standby function ....................................................................................................................... 333 Configuration............................................................................................................................. 334 CSI4 control registers................................................................................................................ 337 Operations................................................................................................................................. 341 11.5 3-Wire Variable-Length Serial I/O (CSI4) ..............................................................................334 CHAPTER 12 A/D CONVERTER ..........................................................................................................346 12.1 12.2 12.3 12.4 Function ..................................................................................................................................346 Configuration ..........................................................................................................................348 Control Registers ...................................................................................................................350 Operation.................................................................................................................................354 12.4.1 12.4.2 12.4.3 Basic operation ......................................................................................................................... 354 Input voltage and conversion result........................................................................................... 358 A/D converter operation mode .................................................................................................. 359 12.5 Low Power Consumption Mode............................................................................................362 12.6 Cautions ..................................................................................................................................362 12.7 How to Read A/D Converter Characteristics Table.............................................................365 CHAPTER 13 DMA FUNCTIONS..........................................................................................................370 13.1 13.2 13.3 13.4 13.5 13.6 Functions ................................................................................................................................370 Transfer Completion Interrupt Request ...............................................................................370 Configuration ..........................................................................................................................371 Control Registers ...................................................................................................................372 Operation.................................................................................................................................378 Cautions ..................................................................................................................................379 CHAPTER 14 RESET FUNCTION ........................................................................................................382 14.1 General ....................................................................................................................................382 14.2 Pin Operations ........................................................................................................................383 14.3 Power-on-Clear Operation.....................................................................................................385 CHAPTER 15 REGULATOR ..................................................................................................................387 15.1 Outline .....................................................................................................................................387 15.2 Operation.................................................................................................................................387 CHAPTER 16 ROM CORRECTION FUNCTION .................................................................................388 16.1 General ....................................................................................................................................388 16.2 ROM Correction Peripheral I/O Registers............................................................................389 User's Manual U14665EJ4V0UD 13 16.2.1 16.2.2 16.2.3 Correction control register (CORCN).........................................................................................389 Correction request register (CORRQ) .......................................................................................389 Correction address registers 0 to 3 (CORAD0 to CORAD3) .....................................................390 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) ................................................ 392 17.1 Features.................................................................................................................................. 392 17.1.1 17.1.2 Erasing unit ...............................................................................................................................392 Write/read time ..........................................................................................................................392 17.2 17.3 17.4 17.5 Writing with Flash Programmer ........................................................................................... 393 Programming Environment .................................................................................................. 396 Communication Mode ........................................................................................................... 397 Pin Connection ...................................................................................................................... 399 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.6 17.6.1 17.6.2 17.6.3 17.6.4 VPP pin .......................................................................................................................................399 Serial interface pin.....................................................................................................................399 RESET pin.................................................................................................................................401 Port pin (including NMI) .............................................................................................................401 Other signal pins........................................................................................................................401 Power supply.............................................................................................................................401 Flash memory control ................................................................................................................402 Flash memory programming mode............................................................................................402 Selection of communication mode.............................................................................................403 Communication command.........................................................................................................403 17.6 Programming Method............................................................................................................ 402 CHAPTER 18 FCAN CONTROLLER ................................................................................................... 405 18.1 Overview of Functions .......................................................................................................... 405 18.2 Configuration ......................................................................................................................... 406 18.3 Internal Registers of FCAN Controller ................................................................................ 408 18.3.1 18.3.2 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.8 18.4.9 Configuration of message buffers..............................................................................................408 List of FCAN registers ...............................................................................................................409 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31)....................................423 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) ......................................425 CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) .................................427 CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7)..........................................429 CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) ...................................................................431 CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) ...........................433 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)........................................435 CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31).....................................437 CAN interrupt pending register (CCINTP) .................................................................................439 18.4 Control Registers................................................................................................................... 423 18.4.10 CAN global interrupt pending register (CGINTP).......................................................................440 18.4.11 CANn interrupt pending register (CnINTP) ................................................................................441 18.4.12 CAN stop register (CSTOP) ......................................................................................................443 18.4.13 CAN global status register (CGST)............................................................................................444 18.4.14 CAN global interrupt enable register (CGIE)..............................................................................447 18.4.15 CAN main clock selection register (CGCS) ...............................................................................448 14 User's Manual U14665EJ4V0UD 18.4.16 CAN time stamp count register (CGTSC).................................................................................. 450 18.4.17 CAN message search start/result register (CGMSS/CGMSR) .................................................. 451 18.4.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) ................................. 453 18.4.19 CANn control register (CnCTRL)............................................................................................... 455 18.4.20 CANn definition register (CnDEF) ............................................................................................. 460 18.4.21 CANn information register (CnLAST) ........................................................................................ 463 18.4.22 CANn error count register (CnERC) .......................................................................................... 464 18.4.23 CANn interrupt enable register (CnIE)....................................................................................... 465 18.4.24 CANn bus active register (CnBA).............................................................................................. 467 18.4.25 CANn bit rate prescaler register (CnBRP)................................................................................. 468 18.4.26 CANn bus diagnostic information register (CnDINF) ................................................................. 471 18.4.27 CANn synchronization control register (CnSYNC) .................................................................... 472 18.5 Cautions Regarding Bit Set/Clear Function ........................................................................474 18.6 Time Stamp Function.............................................................................................................476 18.7 Message Processing..............................................................................................................480 18.7.1 18.7.2 Message transmission............................................................................................................... 480 Message reception .................................................................................................................... 482 18.8 Mask Function ........................................................................................................................483 18.9 Protocol ...................................................................................................................................485 18.9.1 18.9.2 Protocol mode function.............................................................................................................. 485 Message formats....................................................................................................................... 486 18.10 Functions ................................................................................................................................495 18.10.1 Determination of bus priority ..................................................................................................... 495 18.10.2 Bit stuffing ................................................................................................................................. 495 18.10.3 Multiple masters ........................................................................................................................ 495 18.10.4 Multi-cast................................................................................................................................... 495 18.10.5 CAN sleep mode/CAN stop mode function ............................................................................... 496 18.10.6 Error control function ................................................................................................................. 496 18.10.7 Baud rate control function ......................................................................................................... 499 18.11 Operations...............................................................................................................................502 18.11.1 Initialization processing ............................................................................................................. 502 18.11.2 Transmit setting......................................................................................................................... 515 18.11.3 Receive setting.......................................................................................................................... 516 18.11.4 CAN sleep mode ....................................................................................................................... 518 18.11.5 CAN stop mode......................................................................................................................... 520 18.12 Rules for Correct Setting of Baud Rate ...............................................................................521 18.13 Ensuring Data Consistency ..................................................................................................525 18.13.1 Sequential data read ................................................................................................................. 525 18.13.2 Burst read mode........................................................................................................................ 526 18.14 Interrupt Conditions...............................................................................................................527 18.14.1 Interrupts that occur for FCAN controller................................................................................... 527 18.14.2 Interrupts that occur for global CAN interface ........................................................................... 527 18.15 How to Shut Down FCAN Controller ....................................................................................528 18.16 Cautions on Use .....................................................................................................................529 CHAPTER 19 ELECTRICAL SPECIFICATIONS..................................................................................532 19.1 Normal Operation Mode.........................................................................................................533 19.2 Flash Memory Programming Mode (PD70F3079AY and 70F3079Y Only) ......................559 User's Manual U14665EJ4V0UD 15 CHAPTER 20 PACKAGE DRAWINGS ................................................................................................ 560 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS........................................................... 562 APPENDIX A NOTES ON TARGET SYSTEM DESIGN ................................................................... 564 APPENDIX B REGISTER INDEX ......................................................................................................... 566 APPENDIX C INSTRUCTION SET LIST .............................................................................................. 574 APPENDIX D D.1 D.2 REVISION HISTORY ..................................................................................................... 581 Major Revisions in This Edition ........................................................................................... 581 Revision History up to Preceding Edition........................................................................... 581 16 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION The V850/SF1 is a product in the NEC Electronics V850 Series of single-chip microcontrollers designed for low power operation. 1.1 General The V850/SF1 is a 32-bit single-chip microcontroller that includes the V850 Series CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a DMA controller, and features an automotive LAN (FCAN (Full Controller Area Network)). In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850/SF1 has multiplication, saturation operation, and bit manipulation instructions, realized by a hardware multiplier. Table 1-1 shows the outline of the V850/SF1 product lineup. Table 1-1. Product Lineup of V850/SF1 Product Name Commercial Name V850/SF1 Part Number Type Mask ROM ROM Size 128 KB 12 KB On-chip I C 2 RAM Size IC 2 FCAN PD703075AY PD703076AY PD703078AY PD703078Y PD703079AY PD703079Y PD70F3079AY PD70F3079Y 1 channel 2 channels 256 KB 16 KB 1 channel 2 channels Flash memory User's Manual U14665EJ4V0UD 17 CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time 62.5 ns (operating at 16 MHz, external power supply 5 V, regulator output 3.0 V) General-purpose registers CPU features 32 bits x 32 registers Signed multiplication (16 x 16 32): 125 ns (operating at 16 MHz) (able to execute instructions in parallel continuously without creating any register hazards). Saturation operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space 16 MB of linear address space (for programs and data) External expandability: Expandable to 4 MB Memory block allocation function: 2 MB per block Programmable wait function Idle state insertion function * Internal memory PD703075AY, 703076AY (mask ROM: 128 KB/RAM: 12 KB) PD703078AY, 703078Y, 703079AY, 703079Y (mask ROM: 256 KB/RAM: 16 KB) PD70F3079AY, 70F3079Y (flash memory: 256 KB/RAM: 16 KB) 3 V to 5 V interface enabled Bus hold function External wait function * External bus interface 16-bit data bus (address/data multiplexed) Interrupts and exceptions Non-maskable interrupts: 2 sources Maskable interrupts: 41 sources (PD703075AY, 703078AY, 703078Y) 44 sources (PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y) Software exceptions: 32 sources Exception trap: 1 source I/O lines Timer function Total: 84 (12 input ports and 72 I/O ports) 3 V to 5 V interface enabled 16-bit timer: 3 channels (TM0, TM1, TM7) 16-bit timer: 5 channels (TM2 to TM6) Watch timer When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. Watchdog timer: 1 channel Serial interface Asynchronous serial interface (UART) Clocked serial interface (CSI) I2C bus interface (I2C) 8-/16-bit variable-length serial interface CSI/UART: CSI/I C: CSI (8-/16-bit valuable): 2 2 channels 1 channel 1 channel Dedicated baud rate generator: 3 channels 18 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION A/D converter DMA controller ROM correction Regulator 10-bit resolution: 12 channels Internal RAM on-chip peripheral I/O: 6 channels 4 points modifiable 4.0 V to 5.5 V input internal 3.0 V (PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y) 4.5 V to 5.5 V input internal 3.0 V (PD70F3079AY, 70F3079Y) Key return function Clock generator Power-saving functions Automotive LAN Package CMOS structure 4 to 8 pins selectable, falling edge fixed During main clock or subclock operation 5-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXT) HALT/IDLE/STOP modes 2 channels (PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y) 1 channel (PD703075AY, 703078AY, 703078Y) 100-pin plastic LQFP (fine pitch, 14 x 14) 100-pin plastic QFP (14 x 20) All static circuits 1.3 Applications AV equipment Example: Car audio equipment User's Manual U14665EJ4V0UD 19 CHAPTER 1 INTRODUCTION 1.4 Ordering Information (1) Standard products, (A) grade products Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special PD703075AYGC-xxx-8EU PD703075AYGF-xxx-3BA PD703076AYGC-xxx-8EU PD703076AYGF-xxx-3BA PD703078AYGC-xxx-8EU PD703078AYGF-xxx-3BA PD703078YGC-xxx-8EU PD703078YGF-xxx-3BA PD703079AYGC-xxx-8EU PD703079AYGF-xxx-3BA PD703079YGC-xxx-8EU PD703079YGF-xxx-3BA PD70F3079AYGC-8EU PD70F3079AYGF-3BA PD70F3079YGC-8EU PD70F3079YGF-3BA PD703075AYGC(A)-xxx-8EU PD703076AYGC(A)-xxx-8EU PD703078AYGC(A)-xxx-8EU PD703079AYGC(A)-xxx-8EU PD70F3079AYGC(A)-8EU Remark xxx indicates ROM code suffix. Refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation for detailed information on quality grades and recommended applications. 20 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 x 14) * PD703075AYGC-xxx-8EU * PD703076AYGC-xxx-8EU * PD703078AYGC-xxx-8EU * PD703078YGC-xxx-8EU * PD703079AYGC-xxx-8EU * PD703079YGC-xxx-8EU * PD70F3079AYGC-8EU * PD70F3079YGC-8EU * PD703075AYGC(A)-xxx-8EU * PD703076AYGC(A)-xxx-8EU * PD703078AYGC(A)-xxx-8EU * PD703079AYGC(A)-xxx-8EU * PD70F3079AYGC(A)-8EU Notes 1. 2. PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: IC PD70F3079AY, 70F3079Y: VPP (connect to GND0 to GND2 in normal operation mode). CANTX2 and CANRX2 are available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. P01/INTP0 P13/SI1/RXD0 P14/SO1/TXD0 P15/SCK1/ASCK0 P100/KR0/TO7 P101/KR1/TI70 P102/KR2/TI00 P103/KR3/TI01 P104/KR4/TO0 P105/KR5/TI10 P106/KR6/TI11 P107/KR7/TO1 GND2 P110/WAIT P111 P112 P113 P114/CANTX1 P115/CANRX1 P02/INTP1 P116/CANTX2Note 2 P117/CANRX2Note 2 P03/INTP2 XT1 XT2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P80/ANI8 P81/ANI9 P82/ANI10 P83/ANI11 P00/NMI GND0 CPUREG VDD0 X2 X1 RESET CLKOUT IC/VPPNote 1 P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 GND1 P10/SI0/SDA0 P11/SO0 P12/SCK0/SCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 ADCGND ADCVDD P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 P07/INTP6 P34/VM45/TI71 P33/TI5/TO5 P32/TI4/TO4 P31/TI3/TO3 P30/TI2/TO2 P27 P26 P06/INTP5 P25/SCK4 P24/SO4 P23/SI4 P05/INTP4/ADTRG P22/SCK3/ASCK1 P21/SO3/TXD1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P20/SI3/RXD1 P96/HLDRQ P95/HLDAK P94/ASTB PORTGND P93/DSTB P92/R/W P91/UBEN P90/LBEN PORTVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P04/INTP3 User's Manual U14665EJ4V0UD 21 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 x 20) * PD703075AYGF-xxx-3BA * PD703076AYGF-xxx-3BA * PD703078AYGF-xxx-3BA * PD703078YGF-xxx-3BA * PD703079AYGF-xxx-3BA * PD703079YGF-xxx-3BA * PD70F3079AYGF-3BA * PD70F3079YGF-3BA P75/ANI5 P76/ANI6 P77/ANI7 P80/ANI8 P81/ANI9 P82/ANI10 P83/ANI11 P00/NMI GND0 CPUREG VDD0 X2 X1 RESET CLKOUT IC/VPPNote 1 P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P10/SI0/SDA0 P11/SO0 P12/SCK0/SCL0 P01/INTP0 P13/SI1/RXD0 P14/SO1/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P74/ANI4 ADCGND ADCVDD P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 P07/INTP6 P34/VM45/TI71 P33/TI5/TO5 P32/TI4/TO4 P31/TI3/TO3 P30/TI2/TO2 P27 P26 P06/INTP5 P25/SCK4 P24/SO4 P23/SI4 P05/INTP4/ADTRG 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P22/SCK3/ASCK1 P21/SO3/TXD1 PORTGND P20/SI3/RXD1 P96/HLDRQ P95/HLDAK P94/ASTB P93/DSTB P92/R/W P91/UBEN P90/LBEN PORTVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P04/INTP3 GND1 XT2 XT1 Notes 1. 2. PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: IC PD70F3079AY, 70F3079Y: VPP (connect to GND0 to GND2 in normal operation mode). CANTX2 and CANRX2 are available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. 22 P15/SCK1/ASCK0 P100/KR0/TO7 P101/KR1/TI70 P102/KR2/TI00 P103/KR3/TI01 P104/KR4/TO0 P105/KR5/TI10 P106/KR6/TI11 P107/KR7/TO1 GND2 P110/WAIT P111 P112 P113 P114/CANTX1 P115/CANRX1 P02/INTP1 P116/CANTX2Note 2 P117/CANRX2Note 2 P03/INTP2 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION Pin names A16 to A21: AD0 to AD15: ADCGND: ADCVDD ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: Address bus Address/data bus Ground for analog Power supply for analog AD trigger input Analog input Asynchronous serial clock Address strobe P50 to P57: P60 to P65: P70 to P77: P80 to P83: P90 to P96: P100 to P107: P110 to P117: RESET: R/W: RXD0, RXD1: SCK0, SCK1, SCK3, SCK4: SCL0: SDA0: Ground Hold acknowledge Hold request Internally connected External interrupt input Key return Lower byte enable Non-maskable interrupt request Ground for ports Power supply for ports Port 0 Port 1 Port 2 Port 3 Port 4 SI0, SI1, SI3, SI4: SO0, SO1, SO3, SO4: TI00, TI01, TI10, TI11, TI2 to TI5, TI70, TI71: TO0 to TO5, TO7: TXD0, TXD1: UBEN: VDD0: VM45: VPP: WAIT: X1, X2: XT1, XT2: Timer input Timer output Transmit data Upper byte enable Power supply VDD = 4.5 V monitor output Programming power supply Wait Crystal for main clock Crystal for sub-clock Serial output Serial clock Serial clock Serial data Serial input Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Reset Read/write status Receive data CANRX1, CANRX2: FCAN receive data CANTX1, CANTX2: FCAN transmit data CLKOUT: CPUREG: DSTB: GND0, GND1, GND2: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: PORTGND: PORTVDD P00 to P07: P10 to P15: P20 to P27: P30 to P34: P40 to P47: Clock output Regulator control Data strobe User's Manual U14665EJ4V0UD 23 CHAPTER 1 INTRODUCTION 1.6 Function Blocks 1.6.1 Internal block diagram NMI INTP0 to INTP6 TI00,TI01, TI10,TI11, TI70, TI71 TO0,TO1, TO7 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 ROM INTC Note 1 Timer/counter 16-bit timer: TM0, TM1, TM7 16-bit timer: TM2 to TM6 SIO PC 32-bit barrel shifter RAM System registers CPU ROM correction Multiplier 16 x1632 BCU ALU Instruction queue HLDRQ(P96) HLDAK(P95) ASTB(P94) DSTB (P93) R/W (P92) UBEN(P91) LBEN (P90) WAIT(P110) A16 to A21(P60 to P65) AD0 to AD15 (P40 to P47,P50 to P57) Note 2 General-purpose registers 32 bits x 32 SO0 SI0/SDA0 Note 3 SCK0/SCL0 Note 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 CANTX1 CANRX1 CANTX2Note 3 CANRX2Note 3 KR0 to KR7 CSI0/I2C0 CSI1/UART0 CSI3/UART1 Ports Variablelength CSI4 P110 to P117 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P34 P20 to P27 P10 to P15 P00 to P07 A/D converter CG CLKOUT X1 X2 XT1 XT2 RESET FCAN Key return ANI0 to ANI11 ADTRG ADCGND ADCVDD 3.0 V Regulator VDD0 GND0 VM45 PORTVDD PORTGND GND1 GND2 VPPNote 4 ICNote 5 DMAC: 6 ch CPUREG Watch timer Watchdog timer Notes 1. 2. 3. 4. 5. PD703075AY, 703076AY: 128 KB (mask ROM) PD703078AY, 703078Y, 703079AY, 703079Y: 256 KB (mask ROM) PD70F3079AY, 70F3079Y: 256 KB (flash memory) PD703075AY, 703076AY: 12 KB PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y: 16 KB PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y PD70F3079AY, 70F3079Y PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y 24 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue. (3) ROM This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H. ROM can be accessed by the CPU in one clock cycle during instruction fetch. The internal ROM capacity and internal ROM area differ as follows depending on the product. Product Name Internal ROM Capacity 128 KB (mask ROM) 256 KB (mask ROM) 256 KB (flash memory) Internal ROM Area xx000000H to xx01FFFFH xx000000H to xx03FFFFH PD703075AY, 703076AY PD703078AY, 703078Y, 703079AY, 703079Y PD70F3079AY, 70F3079Y (4) RAM The internal RAM capacity and internal RAM area differ as follows depending on the product. RAM can be accessed by the CPU in one clock cycle during data access. Product Name Internal RAM Capacity 12 KB 16 KB Internal RAM Capacity xxFFC000H to xxFFEFFFH xxFFB000H to xxFFEFFFH PD703075AY, 703076AY PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (6) Clock generator (CG) The clock generator includes two types of oscillators: one each for the main clock (fXX) and for the subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, and fXT), and supplies one of them as the operating clock for the CPU (fCPU). (7) Timer/counter An eight-channel 16-bit timer/event counter is equipped, enabling measurement of pulse intervals and frequency as well as programmable pulse output. User's Manual U14665EJ4V0UD 25 CHAPTER 1 INTRODUCTION (8) Watch timer This timer counts the reference time period (0.5 second) for counting the clock (the 32.768 kHz subclock or the 8.388 MHz main clock). At the same time, the watch timer can be used as an interval timer for the main clock. (9) Watchdog timer A watchdog timer is equipped to detect inadvertent program loops, system abnormalities, etc. This timer can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs, and when used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (10) Serial interface (SIO) The V850/SF1 includes four kinds of serial interfaces: an asynchronous serial interface (UART0, UART1), clocked serial interface (CSIn), 8-/16-bit variable-length serial interface (CSI4), and I2C bus interface (I2C0). Up to four channels can be used at the same time. Two of these channels are switchable between UART and CSI and another one is switchable between CSI and I2C (n = 0, 1, 3). For UART0 and UART1, data is transferred via the TXD0, TXD1, RXD0, and RXD1 pins. For CSIn, data is transferred via the SOn, SIn, and SCKn pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins. For I2C0, data is transferred via the SDA0 and SCL0 pins. For UART and CSI4, a dedicated baud rate generator is provided. (11) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive approximation method. (12) DMA controller A six-channel DMA controller is equipped. This controller transfers data between the internal RAM and onchip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. 26 User's Manual U14665EJ4V0UD CHAPTER 1 INTRODUCTION (13) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 I/O 8-bit I/O 6-bit I/O 8-bit I/O 5-bit I/O 8-bit I/O 8-bit I/O 6-bit I/O 8-bit input 4-bit input 7-bit I/O 8-bit I/O 8-bit I/O External bus interface control signal I/O Timer I/O, key return input Wait control, FCAN data I/O External address bus A/D converter analog input Port Function Generalpurpose port Control Function NMI, external interrupt, A/D converter trigger Serial interface Serial interface Timer I/O, VDD = 4.5 V monitor output External address/data bus (14) FCAN controller The FCAN controller is a small-scale digital data transmission system for transferring data between units. A two-channel FCAN controller is incorporated in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y (FCAN1, FCAN2), and a one-channel FCAN controller is incorporated in the PD703075AY, 703078AY, and 703078Y (FCAN1). User's Manual U14665EJ4V0UD 27 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of pins of V850/SF1 are described below, divided into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: ADCVDD, PORTVDD, and VDD0. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply ADCVDD PORTVDD P70 to P77, P80 to P83 P01 to P07, P10 to P15, P20 to P27, P30 to P34, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P100 to P107, P110 to P117 VDD0 P00, RESET, CLKOUT Corresponding Pins 28 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/3) Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P40 P41 P42 P43 P44 P45 P46 P47 I/O No Port 4 8-bit I/O port Input/output can be specified in 1-bit units. I/O No Port 3 5-bit I/O port Input/output can be specified in 1-bit units. TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 VM45/TI71 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 I/O No Port 2 8-bit I/O port Input/output can be specified in 1-bit units. I/O No Port 1 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL No Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5 INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 SI4 SO4 SCK4 - - Remark PULL: On-chip pull-up resistor User's Manual U14665EJ4V0UD 29 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P90 P91 P92 P93 P94 P95 P96 I/O No Port 9 7-bit I/O port Input/output can be specified in 1-bit units. Input No Port 8 4-bit input port Input No Port 7 8-bit input port I/O No Port 6 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL No Port 5 8-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ Remark PULL: On-chip pull-up resistor 30 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 P117 CANTX1 CANRX1 CANTX2 Note I/O I/O PULL Yes Port 10 8-bit I/O port Function Alternate Function KR0/TO7 KR1/TI7 KR2/TI00 KR3/TI01 KR4/TO0 KR5/TI10 KR6/TI11 KR7/TO1 Input/output can be specified in 1-bit units. I/O No Port 11 8-bit I/O port Input/output can be specified in 1-bit units. WAIT - - - CANRX2 Note Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y Remark PULL: On-chip pull-up resistor User's Manual U14665EJ4V0UD 31 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name A16 to A21 AD0 to AD7 AD8 to AD15 ADCGND ADCVDD ADTRG ANI0 to ANI7 ANI8 to ANI11 ASCK0 ASCK1 ASTB CANRX1 CANRX2 CANTX1 CANTX2 CLKOUT CPUREG DSTB GND0 to GND2 HLDAK HLDRQ IC INTP0 to INTP3 INTP4 INTP5 INTP6 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 LBEN NMI Output Input No No External data bus's lower byte enable signal output Non-maskable interrupt request input Input Yes External interrupt request input (digital noise elimination for remote control) Key return input Output Input Input Output Output Output - Output - Output Input - Input - - No - No No - Yes No No External address strobe signal output CAN1 receive data input CAN2 receive data input Note 1 I/O Output I/O PULL No No Function Higher address bus used for external memory expansion 16-bit multiplexed address/data bus used for external memory expansion Ground potential for A/D converter Power supply pin and reference voltage pin for A/D converter A/D converter external trigger input Analog input to A/D converter Alternate Function P60 to P65 P40 to P47 P50 to P57 - - P05/INTP4 P70 to P77 P80 to P83 - - Input Input - - No No Input No Baud rate clock input for UART0 and UART1 P15/SCK1 P22/SCK3 P94 P115 P117 P114 P116 - - P93 - P95 P96 - P01 to P04 P05/ADTRG P06 P07 P100/TO7 P101/TI70 P102/TI00 P103/TI01 P104/TO0 P105/TI10 P106/TI11 P107/TI01 P90 P00 CAN1 transmit data output CAN2 transmit data output Note 1 Internal system clock output Connection of regulator output stabilizing capacitance External data strobe signal output Ground potential Bus hold acknowledge output Bus hold request input Internally connected Note 2 External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination) Notes 1. Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y 2. Available only in the PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, and 703079Y Remark PULL: On-chip pull-up resistor 32 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name PORTGND PORTVDD RESET R/W RXD0 RXD1 SCK0 SCK1 SCK3 SCK4 SCL0 SDA0 SI0 SI1 SI3 SI4 SO0 SO1 SO3 SO4 TI00 TI01 TI10 TI11 TI2 TI3 TI4 TI5 TI70 TI71 TO0 TO1 TO2 TO3 TO4 TO5 TO7 Yes No Output Yes No Yes No Input Yes Serial transmit data output for variable-length CSI4 (3-wire type) Shared as external capture trigger input and external count clock input for TM0 External capture trigger input for TM0 External count clock input/external capture trigger input for TM1 External capture trigger input for TM1 External count clock input for TM2 External count clock input for TM3 External count clock input for TM4 External count clock input for TM5 External count clock input/external capture trigger input for TM7 External capture trigger input for TM7 Pulse signal output for TM0 Pulse signal output for TM1 Pulse signal output for TM2 Pulse signal output for TM3 Pulse signal output for TM4 Pulse signal output for TM5 Pulse signal output for TM7 Output No Serial receive data input (3-wire type) for variable-length CSI4 Serial transmit data output (3-wire type) for CSI0, CSI1, CSI3 I/O I/O Input No No No Serial clock I/O for variable-length CSI4 (3-wire type) Serial clock I/O for I C0 Serial transmit/receive data I/O for I C0 Serial receive data input (3-wire type) for CSI0, CSI1, CSI3 2 2 I/O - - Input Output Input PULL - - - No No Function Ground potential for port output Positive power supply for port output System reset input External read/write status output Serial receive data input for UART0 and UART1 Alternate Function - - - P92 P13/SI1 P20/SI3 I/O No Serial clock I/O (3-wire type) for CSI0, CSI1, CSI3 P12/SCL0 P15/ASCK0 P22/ASCK1 P25 P12/SCK0 P10/SI0 P10/SDA0 P13/RXD0 P20/RXD1 P23 P11 P14/TXD0 P21/TXD1 P24 P102/KR2 P103/KR3 P105/KR5 P106/KR6 P30/TO2 P31/TO3 P32/TO4 P33/TO5 P101/KR1 P34/VM45 P104/KR4 P107/KR7 P30/TI2 P31/TI3 P32/TI4 P33/TI5 P100/KR0 Remark PULL: On-chip pull-up resistor User's Manual U14665EJ4V0UD 33 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name TXD0 TXD1 UBEN VDD0 VM45 VPP Output - Output - No - No - Higher byte enable signal output for external data bus Positive power supply pin VDD = 4.5 V monitor output High-voltage application pin for program write/verify (PD70F3079AY and 70F3079Y only) Control signal input for inserting wait in bus cycle Resonator connection for main clock P110 - - No Resonator connection for subclock - - P34/TI71 - I/O Output PULL No Function Serial transmit data output for UART0 and UART1 Alternate Function P14/SO1 P21/SO3 P91 - WAIT X1 X2 XT1 XT2 Input Input - Input - Yes No Remark PULL: On-chip pull-up resistor 34 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operating states of various pins are described below with reference to the operation mode. Table 2-2. Pin Operating State According to Operation Mode Operation Mode Pin AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB ASTB HLDRQ HLDAK WAIT CLKOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - Note 4 Reset Note 1 HALT Mode/ Idle State Hi-Z Held Held H H H Operating Operating - Operating Note 5 IDLE Mode/ STOP Mode Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - L Bus Hold Busy Cycle Inactive Note 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating L - Operating Note 5 Hi-Z Held Note 3 Held Note 3 H H H Operating Operating - Operating Note 5 Notes 1. Pins (except the CLKOUT pin) are used as port pins (input mode) after reset. 2. The bus cycle inactivation timing occurs when the internal memory area is specified by the program counter (PC) in the external expansion mode. 3. * When the external memory area has not been accessed even once after reset is released and the external expansion mode is set: Undefined * When the bus cycle is inactivated after access to the external memory area, or when the external memory area has not been accessed even once after the external expansion mode is released and set again: The state of the external bus cycle when the external memory area accessed last is held. 4. CLKOUT pin status during reset period <1> PD703078Y, 703079Y, 70F3079Y: Hi-Z <2> PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY: L (insertion of pull-down resistor) * A pull-down resistor is inserted only during the reset period. A low level is output after reset is released (PSC register initial setting). * After reset is released, do not input a high level to the CLKOUT pin. If a high level is input, the subsequent operation cannot be guaranteed. * Pull-down resistor: 40 k (TYP.) 5. Low level (L) when in clock output inhibit mode Remark Hi-Z: Held: L: H: -: High impedance State is held during previously set external bus cycle Low-level output High-level output Input not sampled User's Manual U14665EJ4V0UD 35 CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (port 0) *** 3-state I/O P00 to P07 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P00 to P07 can also function as I/O port pins and can also function as NMI inputs, external interrupt request inputs, and external triggers for the A/D converter. The pin's valid edge is specified by the EGP0 and EGN0 registers. (a) Port function P00 to P07 can be set to input or output in 1-bit units according to the contents of the port 0 mode register (PM0). (b) Alternate functions (i) NMI (non-maskable interrupt request) *** input This is a non-maskable interrupt request signal input pin. (ii) INTP0 to INTP6 (external interrupt input) *** input These are external interrupt request input pins. (iii) ADTRG (AD trigger input) *** input This is the A/D converter's external trigger input pin. This pin is controlled by A/D converter mode register 1 (ADM1). (2) P10 to P15 (port 1) *** 3-state I/O P10 to P15 constitute a 6-bit I/O port in which input and output can be specified in 1-bit units. P10 to P15 can also function as input or output pins for the serial interface. P10 and P12 can be selected as normal output or N-ch open-drain output. (a) Port function P10 to P15 can be set to input or output in 1-bit units according to the contents of the port 1 mode register (PM1). (b) Alternate function (i) SI0, SI1 (serial input 0, 1) *** input These are the serial receive data input pins of CSI0 and CSI1. (ii) SO0, SO1 (serial output 0, 1) *** output These are the serial transmit data output pins of CSI0 and CSI1. (iii) SCK0, SCK1 (serial clock 0, 1) *** 3-state I/O These are the serial clock I/O pins for CSI0 and CSI1. (iv) SDA0 (serial data 0) *** I/O This is the serial transmit/receive data I/O pin for I2C0. 36 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (v) SCL0 (serial clock 0) *** I/O This is the serial clock I/O pin for I2C0. (vi) RXD0 (receive data 0) *** input This is the serial receive data input pin of UART0. (vii) TXD0 (transmit data 0) *** output This is the serial transmit data output pin of UART0. (viii) ASCK0 (asynchronous serial clock 0) *** input This is the serial baud rate clock input pin of UART0. (3) P20 to P27 (port 2) *** 3-state I/O P20 to P27 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P20 to P27 can also function as input or output pins for the serial interface. (a) Port function P20 to P27 can be set to input or output in 1-bit units according to the contents of the port 2 mode register (PM2). (b) Alternate functions (i) SI3, SI4 (serial input 3, 4) *** input These are the serial receive data input pins of CSI3 and CSI4. (ii) SO3, SO4 (serial output 3, 4) *** output These are the serial transmit data output pins of CSI3 and CSI4. (iii) SCK3, SCK4 (serial clock 3, 4) *** 3-state I/O These are the serial clock I/O pins of CSI3 and CSI4. (iv) RXD1 (receive data 1) ... input This is the serial receive data input pin of UART1. (v) TXD1 (transmit data 1) ... output This is the serial transmit data output pin of UART1. (vi) ASCK1 (asynchronous serial clock 1) ... input This is the serial baud rate clock input pin of UART1. User's Manual U14665EJ4V0UD 37 CHAPTER 2 PIN FUNCTIONS (4) P30 to P34 (port 3) *** 3-state I/O P30 to P34 constitute a 5-bit I/O port in which input and output can be specified in 1-bit units. P30 to P34 can also function as input or output pins for the timer/counter, and VDD = 4.5 V monitor output. (a) Port function P30 to P34 can be set to input or output in 1-bit units according to the contents of the port 3 mode register (PM3). (b) Alternate functions (i) TI2, TI3, TI4, TI5, TI71 (timer input 2, 3, 4, 5, 71) *** input These are the external count clock input pins of timers 2, 3, 4, 5, and 7. (ii) TO2, TO3, TO4, TO5 (timer output 2, 3, 4, 5) *** output These are the pulse signal output pins of timers 2, 3, 4, and 5. (iii) VM45 (VDD = 4.5 V monitor output) *** output This is the VDD = 4.5 V monitor output pin. (5) P40 to P47 (port 4) *** 3-state I/O P40 to P47 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P40 to P47 can also function as a time division address/data bus (AD0 to AD7) when memory is expanded externally. (a) Port function P40 to P47 can be set to input or output in 1-bit units according to the contents of the port 4 mode register (PM4). (b) Alternate function (external expansion mode) P40 to P47 can be set as AD0 to AD7 according to the contents of the memory expansion mode register (MM). (i) AD0 to AD7 (address/data 0 to 7) *** 3-state I/O These pins comprise a multiplexed address/data bus that is used for external access. At the address timing (T1 state), these pins operate as the AD0 to AD7 (22-bit address) output pins. At the data timing (T2, TW, T3), they operate as the lower 8-bit I/O bus pins for 16-bit data. The output changes in synchronization with the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle as inactive, these pins go into a high-impedance state. 38 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (6) P50 to P57 (port 5) *** 3-state I/O P50 to P57 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P50 to P57 can also function as a time division address/data bus (AD8 to AD15) when memory is expanded externally. (a) Port function P50 to P57 can be set to input or output in 1-bit units according to the contents of the port 5 mode register (PM5). (b) Alternate function (external expansion mode) P50 to P57 can be specified as AD8 to AD15 according to the contents of the memory expansion mode register (MM). (i) AD8 to AD15 (address/data 8 to 15) *** 3-state I/O These pins comprise a multiplexed address/data bus that is used for external access. At the address timing (T1 state), these pins operate as the AD8 to AD15 (22-bit address) output pins. At the data timing (T2, TW, T3), they operate as the higher 8-bit I/O bus pins for 16-bit data. The output changes in synchronization with the rising edge of the clock in each state within the bus cycle. When the timing sets the bus cycle as inactive, these pins go into a high-impedance state. (7) P60 to P65 (port 6) *** 3-state I/O P60 to P65 constitute a 6-bit I/O port in which input and output can be specified in 1-bit units. P60 to P65 can also function as an address bus (A16 to A21) when memory is expanded externally. During 8-bit access of port 6, the higher 2 bits are ignored when writing, and are read as "00" when reading. (a) Port function P60 to P65 can be set to input or output in 1-bit units according to the contents of the port 6 mode register (PM6). (b) Alternate function (external expansion mode) P60 to P65 can be set as A16 to A21 according to the contents of the memory expansion mode register (MM). (i) A16 to A21 (address 16 to 21) *** output These pins comprise an address bus that is used for external access. These pins operate as the higher 6-bit address output pins within a 22-bit address. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus cycle's address is retained. User's Manual U14665EJ4V0UD 39 CHAPTER 2 PIN FUNCTIONS (8) P70 to P77 (port 7), P80 to P83 (port 8) *** input P70 to P77 constitute an 8-bit input-only port in which all pins are fixed to input. P80 to P83 constitute a 4-bit input-only port in which all pins are fixed to input. P70 to P77 and P80 to P83 can also function as analog input pins for the A/D converter. However, they cannot be switched between input ports and analog input pins. (a) Port function P70 to P77 and P80 to P83 are input-only pins. (b) Alternate function P70 to P77 also function as pins ANI0 to ANI7 and P80 to P83 also function as ANI8 to ANI11, but these alternate functions are not switchable. (i) ANI0 to ANI11 (analog input 0 to 11) *** input These are analog input pins for the A/D converter. Connect a capacitor between ADCVDD and ADCGND to prevent noise-related operation faults. Also, do not apply voltage that is outside the range for ADCVDD and ADCGND to pins that are being used as inputs for the A/D converter. If it is possible for noise above the ADCVDD range or below the ADCGND to enter, clamp these pins using a diode that has a small VF value. (9) P90 to P96 (port 9) *** 3-state I/O P90 to P96 constitute a 7-bit I/O port in which input and output can be specified in 1-bit units. P90 to P96 can also function as control signal output pins, and bus hold control signal output pins when memory is expanded externally. During 8-bit access of port 9, the MSB is ignored when writing and is read as "0" when reading. (a) Port function P90 to P96 can be set to input or output in 1-bit units according to the contents of the port 9 mode register (PM9). (b) Alternate functions (external expansion mode) P90 to P96 can be set to operate as control signal outputs for external memory expansion according to the contents of the memory expansion mode register (MM). (i) LBEN (lower byte enable) *** output This is the lower byte enable signal output pin for an external 16-bit data bus. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the previous bus cycle's status is retained. 40 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (ii) UBEN (upper byte enable) *** output This is the higher byte enable signal output pin for an external 16-bit data bus. During byte access of even-numbered addresses, these pins are set as inactive (high level). the bus cycle as inactive, the previous bus cycle's status is retained. Access Word access Halfword access Byte access Even-numbered address Odd-numbered address UBEN 0 0 1 0 LBEN 0 0 0 1 AD0 0 0 0 1 The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets (iii) R/W (read/write status) *** output This is an output pin for the status signal that indicates whether the bus cycle is a read cycle or write cycle during external access. High level is set during the read cycle and low level is set during the write cycle. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. High level is set when the timing sets the bus cycle as inactive. (iv) DSTB (data strobe) *** output This is an output pin for the external data bus's access strobe signal. Output becomes active (low level) during the T2 and TW states of the bus cycle. Output becomes inactive (high level) when the timing sets the bus cycle as inactive. (v) ASTB (address strobe) *** output This is an output pin for the external address bus's latch strobe signal. Output becomes active (low level) in synchronization with the falling edge of the clock during the T1 state of the bus cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the T3 state of the bus cycle. Output becomes inactive when the timing sets the bus cycle as inactive. (vi) HLDAK (hold acknowledge) *** output This is an output pin for the acknowledge signal that indicates high impedance status for the address bus, data bus, and control bus when the V850/SF1 receives a bus hold request. The address bus, data bus, and control bus are set to high impedance when this signal is active. (vii) HLDRQ (hold request) *** input This is the input pin by which an external device requests the V850/SF1 to release the address bus, data bus, and control bus. This pin can be input asynchronously to CLKOUT. When this pin is active, the address bus, data bus, and control bus are set to high impedance. The HLDAK signal is then set as active and the bus is released. This occurs either when the V850/SF1 completes execution of the current bus cycle or immediately if no bus cycle is being executed. User's Manual U14665EJ4V0UD 41 CHAPTER 2 PIN FUNCTIONS (10) P100 to P107 (port 10) *** 3-state I/O P100 to P107 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P100 to P107 can also function as timer/counter I/O pins and key return input pins. (a) Port function P100 to P107 can be set to input or output in 1-bit units according to the contents of the port 10 mode register (PM10). (b) Alternate function (i) KR0 to KR7 (key return 0 to 7) ... input These are key interrupt input pins. Their operations are specified by the key return mode register (KRM). (ii) TI00, TI01, TI10, TI11, TI70 (timer input 00, 01, 10, 11, 70) ... input These are external count clock input pins for timers 0, 1, and 7. (iii) TO0, TO1, TO7 (timer output 0, 1, 7) ... output These are pulse signal output pins for timers 0, 1, and 7. (11) P110 to P117 (port 11) *** 3-state I/O P110 to P117 constitute an 8-bit I/O port in which input and output can be specified in 1-bit units. P110 to P117 can also function as FCAN data I/O pins and the control signal (WAIT) that inserts waits into the bus cycle. (a) Port function P110 to P117 can be set to input or output in 1-bit units according to the contents of the port 11 mode register (PM11). (b) Alternate functions (i) WAIT (wait) *** input This is an input pin for the control signal used to insert waits into the bus cycle. This pin is sampled at the falling edge of the clock during the T2 or TW state of the bus cycle. ON/OFF switching of the wait function is performed by the port alternate function control register (PAC). (ii) CANRX1, CANRX2 (CAN receive data 1, 2) *** input These are data input signals for CAN1 and CAN2. CANRX2 is available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. (iii) CANTX1, CANTX2 (CAN transmit data 1, 2) *** output These are data output signals for CAN1 and CAN2. CANTX2 is available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. 42 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (12) RESET (reset) *** input RESET input is an asynchronous input signal and has a constant low level width regardless of the operating clock's status. When this signal is input, a system reset is executed as the first priority ahead of all other operations. In addition to being used for ordinary initialization/start operations, this pin can also be used to cancel a standby mode (HALT, IDLE, or STOP mode). (13) X1, X2 (crystal) These pins are used to connect the resonator that generates the main clock. (14) XT1, XT2 (crystal for subclock) These pins are used to connect the resonator that generates the subclock. (15) ADCVDD (analog power supply) This is the analog positive power supply pin for the A/D converter and alternate-function ports. (16) ADCGND (ground for analog) This is the ground pin for the A/D converter and alternate-function ports. (17) CPUREG (regulator control) This is the regulator pin for the CPU power supply. Connect this pin to GND0 to GND2 via a capacitor of 1 F (recommended value). (18) CLKOUT (clock out) *** output This pin outputs the bus clock generated internally. (19) PORTVDD (power supply for ports) This is the positive power supply pin for I/O ports and alternate-function pins. (20) PORTGND (ground for ports) This is the ground pin for I/O ports and alternate-function pins (except for the alternate-function ports of the bus interface). (21) VDD0 (power supply) This is the positive power supply pin. All VDD0 pins should be connected to a positive power supply. (22) GND0 to GND2 (ground) These are the ground pins. All GND0 to GND2 pins should be grounded. (23) VPP (programming power supply) This is the positive power supply pin used for flash memory programming mode. This pin is used in the PD70F3079AY and 70F3079Y. Connect to GND0 to GND2 in normal operation mode. (24) IC (internally connected) This is an internally connected pin used in the PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, and 703079Y. Connect directly to GND0 to GND2 in normal operation mode. User's Manual U14665EJ4V0UD 43 CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins (1/2) Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply P00 NMI 8 VDD0 Input: Independently connect to VDD0 or GND0 to GND2 via a resistor. Output: Leave open. P01 to P04 P05 P06, P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 to P33 P34 P40 to P47 P50 to P57 P60 to P65 P70 to P77 P80 to P83 P90 P91 P92 P93 P94 P95 P96 INTP0 to INTP3 INTP4/ADTRG INTP5, INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 SI4 SO4 SCK4 - - TI2/TO2 to TI5/TO5 VM45/TI71 AD0 to AD7 AD8 to AD15 A16 to A21 ANI0 to ANI7 ANI8 to ANI11 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ 5 5 5 9 9 5 PORTVDD PORTVDD PORTVDD ADCVDD ADCVDD PORTVDD Independently connect to ADCVDD or ADCGND via a resistor. Independently connect to PORTVDD or PORTGND via a resistor. Output: Leave open. Input: 5 8 PORTVDD 5 8 10 5 10 8 5 8 8 5 8 PORTVDD PORTVDD PORTVDD Input: Independently connect to PORTVDD or PORTGND via a resistor. Output: Leave open. Recommended Connection Method 44 User's Manual U14665EJ4V0UD CHAPTER 2 PIN FUNCTIONS (2/2) Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 to P113 P114 P115 P116 P117 CLKOUT RESET X1 X2 XT1 XT2 VPP IC Note 2 Recommended Connection Method KR0/TO7 KR1/TI70 KR2/TI00 KR3/TI01 KR4/TO0 KR5/TI10 KR6/TI11 KR7/TO1 WAIT - CANTX1 CANRX1 CANTX2 Note 1 8-A PORTVDD Independently connect to PORTVDD or PORTGND via a resistor. When connecting to PORTGND, disconnect onchip pull-up resistors by software. Output: Leave open. Input: 5 PORTVDD 5 8 5 8 4 2 - - - - - - - - - - - - - VDD0 VDD0 - - - - - - - - - - - - - Leave open. - - - Connect to GND0 to GND2 via a resistor. Leave open. Connect to GND0 to GND2. Connect directly to GND0 to GND2. - - - - - - - CANRX2 Note 1 - - - - - - - - - - - - - - - Note 3 CPUREG VDD0 GND0 to GND2 ADCVDD ADCGND PORTVDD PORTGND Notes 1. PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y 2. PD70F3079AY and 70F3079Y 3. PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, and 703079Y User's Manual U14665EJ4V0UD 45 CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 8-A VDD IN Pullup enable Data P-ch VDD P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch Type 4 Type 9 VDD Data P-ch P-ch IN N- ch + - Comparator OUT VREF (threshold voltage) Output disable N-ch Input enable Push-pull output that can be set to high impedance output (both P-ch and N-ch off). Type 5 Type 10 V DD V DD Data Data P-ch P-ch IN/OUT IN/OUT Output Output disable disable Input enable Input enable N- ch N- ch Open drain Output disable Data VDD P-ch IN/OUT N-ch Type 8 VDD Data P-ch IN/OUT Output disable N-ch 46 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS The CPU of the V850/SF1 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features * * * * * * * * * * Minimum instruction execution time: Address space: 16 MB linear Thirty-two 32-bit general-purpose registers Internal 32-bit architecture Five-stage pipeline control Multiplication/division instructions Saturated operation instructions One-clock 32-bit shift instruction Load/store instructions with long/short format Four types of bit manipulation instructions * * * * 62.5 ns (@ 16 MHz internal operation) SET1 CLR1 NOT1 TST1 User's Manual U14665EJ4V0UD 47 CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers in the V850/SF1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Series Architecture User's Manual. Figure 3-1. CPU Register Set Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Element pointer (EP) Link pointer (LP) Stack pointer (SP) Global pointer (GP) Text pointer (TP) 0 Zero register Reserved for address register System register set 31 EIPC EIPSW Exception/interrupt PC Exception/interrupt PSW 0 31 FEPC FEPSW Fatal error PC Fatal error PSW 0 31 ECR Exception cause register 0 31 PSW Program status word 0 31 PC Program counter 0 48 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost. The contents must be restored to the registers after the registers have been used. r2 may be used by the real-time OS. r2 can be used as a variable register when the real-time OS that is used does not use r2. Table 3-1. Program Registers Name r0 r1 r2 r3 r4 r5 r6 to r29 r30 r31 PC Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate Operation Address/data variable register (when r2 is not used by the real-time OS being used) Stack pointer Global pointer Text pointer Address/data variable registers Element pointer Link pointer Program counter Base pointer when memory is accessed Used by compiler when calling functions Holds instruction address during program execution Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area Note Note Area in which program code is mapped. (2) Program counter (PC) This register holds the address of the instruction under execution. The lower 24 bits of this register are valid, and bits 31 to 24 are fixed to 0. If a carry occurs from bit 23 to 24, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed. After reset: 00000000H 31 PC Fixed to 0 24 23 Instruction address under execution 1 0 0 User's Manual U14665EJ4V0UD 49 CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers No. 0 1 System Register Name EIPC EIPSW Usage Interrupt status saving registers Operation These registers save the PC and PSW when an exception or interrupt occurs. Because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. NMI status saving registers These registers save the PC and PSW when NMI occurs. Because only one set of these registers is available, their contents must be saved when multiple interrupts are enabled. Interrupt source register If an exception, maskable interrupt, or NMI occurs, this register will hold information referencing the interrupt source. The higher 16 bits of this register are called FECC, to which the exception code of NMI is set. The lower 16 bits are called EICC, to which the exception code of the exception/interrupt is set. 5 PSW Program status word The program status word is a collection of flags that indicate the program status (instruction execution result) and CPU status. 6 to 31 Reserved 2 3 FEPC FEPSW 4 ECR To read/write these system registers, specify a system register number, indicated by the system register load/store instruction (LDSR or STSR instruction). (1) Interrupt source register (ECR) After reset: 00000000H 31 ECR FECC 16 15 EICC 0 FECC EICC Exception code of NMI (For exception code, refer to Table 7-1.) Exception code of exception/interrupt 50 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (2) Program status word (PSW) (1/2) After reset: 00000020H 31 PSW RFU 8 7 NP 6 EP 5 4 3 2 OV 1 S 0 Z ID SAT CY RFU Reserved field (fixed to 0). NP 0 1 Non-maskable interrupt (NMI) servicing status NMI servicing not under execution. NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables multiple interrupts. For details, refer to 7.2.3 NP flag. EP 0 1 Exception processing status Exception processing not under execution. Exception processing under execution. This flag is set (1) when an exception is generated. Interrupt requests can be acknowledged when this bit is set. For details, refer to 7.4.3 EP flag. ID 0 1 Maskable interrupt servicing specification Maskable interrupt acknowledgement enabled (EI). Maskable interrupt acknowledgement disabled (DI). This flag is set (1) when a maskable interrupt request is acknowledged. For details, refer to 7.3.6 ID flag. SAT 0 Note Saturation detection of operation result of saturation operation instruction Not saturated. This flag is not cleared (0) if the result of saturated operation instruction execution is not saturated while this flag is set (1). To clear (0) this flag, write the PSW directly. 1 Saturated. CY 0 1 Detection of carry or borrow of operation result Overflow has not occurred. Overflow occurred. OV Note Detection of overflow during operation Overflow has not occurred. Overflow occurred. 0 1 User's Manual U14665EJ4V0UD 51 CHAPTER 3 CPU FUNCTIONS (2/2) S Note Detection of operation result positive/negative The operation result was positive or 0. The operation result was negative. 0 1 Z 0 1 Detection of operation result zero The operation result was not 0. The operation result was 0. Note The result of a saturation-processed operation is determined by the contents of the OV and S bits in the saturation operation. Simply setting (1) the OV bit will set (1) the SAT bit in a saturation operation. Status of operation result SAT Maximum positive value exceeded Maximum negative value exceeded Positive (not exceeding the maximum) Negative (not exceeding the maximum) 1 1 Retains the value before operation Flag status OV 1 1 0 S 0 1 0 1 Saturation-processed operation result 7FFFFFFFH 80000000H Operation result itself 52 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes The V850/SF1 has the following operation modes. (1) Normal operation mode (single-chip mode) After the system has been released from the reset status, the pins related to the bus interface are set to port mode, execution branches to the reset entry address of the internal ROM, and instruction processing written in the internal ROM is started. However, external expansion mode, in which an external device is connected to external memory area, is enabled by setting in the memory expansion mode register (MM) via an instruction. (2) Flash memory programming mode This mode is provided only in the PD70F3079AY and 70F3079Y. The internal flash memory is programmable or erasable when the VPP voltage is applied to the VPP pin. VPP 0 7.8 V VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited User's Manual U14665EJ4V0UD 53 CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space The CPU of the V850/SF1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear address space (program space) of up to 16 MB is supported. The CPU address space is shown below. Figure 3-2. CPU Address Space CPU address space FFFFFFFFH Data area (4 GB linear) 01000000H 00FFFFFFH Program area (16 MB linear) 00000000H 54 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.4.2 Images A 16 MB physical address space is seen as 256 images in the 4 GB CPU address space. In other words, the same 16 MB physical address space is accessed regardless of the values of bits 31 to 24 of the CPU address. The images of the addressing space are shown below. The physical address xx000000H can be seen as CPU address 00000000H, and in addition, can be seen as addresses 01000000H, 02000000H, ... FE000000H, FF000000H. This is because the higher 8 bits of a 32-bit CPU address are ignored and the CPU address is only accessed as a 24-bit physical address. Figure 3-3. Images on Address Space CPU address space FFFFFFFFH Image FF000000H FEFFFFFFH Image Physical address space FE000000H FDFFFFFFH Image (Access prohibited) 02000000H 01FFFFFFH Internal ROM On-chip peripheral I/O Internal RAM xxFFFFFFH xx000000H Image 01000000H 00FFFFFFH Image 00000000H User's Manual U14665EJ4V0UD 55 CHAPTER 3 CPU FUNCTIONS 3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to 24 as a result of a branch address calculation, the higher 8 bits ignore the carry or borrow and remain 0. Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address 00FFFFFFH are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. Figure 3-4. Program Space Program space 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space (+) direction (-) direction (2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address FFFFFFFFH are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. Figure 3-5. Data Space Data space FFFFFFFEH FFFFFFFFH 00000000H 00000001H Data space (+) direction (-) direction 56 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V850/SF1 reserves areas as shown below. Figure 3-6. Memory Map Single-chip mode xxFFFFFFH On-chip peripheral I/O area xxFFF000H xxFFEFFFH Internal RAM area xxFF8000H xxFF7FFFH Single-chip mode (external expansion mode) On-chip peripheral I/O area 4 KB Internal RAM area 28 KB FCAN address area FCAN address area External memory area 16 MB xx100000H xx0FFFFFH Internal flash memory/ ROM area Internal flash memory/ ROM area 1 MB xx000000H User's Manual U14665EJ4V0UD 57 CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM/internal flash memory area An area of 1 MB maximum is reserved for the internal ROM/internal flash memory area. (a) Memory map <1> PD703075AY, 703076AY 128 KB is provided at addresses xx000000H to xx01FFFFH. Addresses xx020000H to xx0FFFFFH are access-prohibited area. Figure 3-7. Internal ROM Area (128 KB) xx0FFFFFH Access-prohibited area xx020000H xx01FFFFH xx000000H Internal ROM <2> PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y 256 KB is provided at addresses xx000000H to xx03FFFFH. Addresses xx040000H to xx0FFFFFH are access-prohibited area. Figure 3-8. Internal ROM/Internal Flash Memory Area (256 KB) xx0FFFFFH Access-prohibited area xx040000H xx03FFFFH Internal ROM/ internal flash memory xx000000H 58 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS Interrupt/exception table The V850/SF1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written at that memory address is executed. corresponding addresses are shown below. Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Table 00000000H 00000010H 00000020H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H Start Address of Interrupt/Exception Table 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H The sources of interrupts/exceptions, and the Interrupt/Exception Source RESET NMI INTWDT TRAP0n (n = 0 to F) TRAP1n (n = 0 to F) ILGOP INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI4 INTAD INTDMA0 INTDMA1 INTDMA2 INTTM00 INTTM01 INTTM10 INTTM11 INTTM2 INTTM3 Interrupt/Exception Source INTTM4 INTTM5 INTWTM INTWTNI INTIIC0/INTCSI0 INTSER0 INTSR0/INTCSI1 INTST0 INTKR INTCE1 INTCR1 INTCT1 INTICME INTTM6 INTTM70 INTTM71 INTSER1 INTSR1/INTCSI3 INTST1 INTDMA3 INTDMA4 INTDMA5 INTCE2 INTCT2 Note Note INTCR2 Note Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. User's Manual U14665EJ4V0UD 59 CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area An area of up to 28 KB is reserved for the internal RAM. (a) PD703075AY, 703076AY 12 KB is provided at addresses xxFFC000H to xxFFEFFFH. Addresses xxFF8000H to xxFFBFFFH are access-prohibited area. Figure 3-9. Internal RAM Area (12 KB) xxFFEFFFH Internal RAM xxFFC000H xxFFBFFFH Access-prohibited area xxFF8000H (b) PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y 16 KB is provided at addresses xxFFB000H to xxFFEFFFH. Addresses xxFF8000H to xxFFAFFFH are access-prohibited area. Figure 3-10. Internal RAM Area (16 KB) xxFFEFFFH Internal RAM xxFFB000H xxFFAFFFH Access-prohibited area xxFF8000H 60 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area The 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. In the V850/SF1, the 1 KB area of addresses FFF000H to FFF3FFH is provided as a physical on-chip peripheral I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH). Peripheral I/O registers associated with functions such as operation mode specification and state monitoring for the on-chip peripherals are all memory-mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Figure 3-11. On-Chip Peripheral I/O Area xxFFFFFFH Image xxFFFC00H xxFFFBFFH Physical on-chip peripheral I/O Image xxFFF800H xxFFF7FFH Image Peripheral I/O 3FFH 000H xxFFF400H xxFFF3FFH Image xxFFF000H Cautions 1. The least significant bit of an address is not decoded. If an odd address (2n + 1) in the peripheral I/O area is referenced (accessed in byte units), the register at an even address (2n) will be accessed. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined, if the access is a read operation. If a write access is made, only the data in the lower 8 bits is written to the register. 3. If a register at address n that can be accessed only in halfword units is accessed in word units, the operation is replaced with two halfword operations. The first operation (lower 16 bits) accesses the register at address n and the second operation (higher 16 bits) accesses the register at address n + 2. 4. If a register at address n that can be accessed in word units is accessed in word units, the operation is replaced with two halfword operations. The first operation (lower 16 bits) accesses the register at address n and the second operation (higher 16 bits) accesses the register at address n + 2. 5. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. User's Manual U14665EJ4V0UD 61 CHAPTER 3 CPU FUNCTIONS (4) External memory The V850/SF1 can use an area of up to 16 MB (xx100000H to xxFF7FFFH) for external memory area (in singlechip mode: external expansion). 64 KB, 256 KB, 1 MB, or 4 MB of physical external memory can be allocated when the external expansion mode is specified. In the area of other than the physical external memory, the image of the physical external memory can be seen. The internal RAM area and on-chip peripheral I/O area are not subject to external memory access. Caution Addresses xxnFF800H to xxnFFFFFH (n = 3, 7, B) constitute an FCAN address area and are therefore access-prohibited. Figure 3-12. External Memory Area (When Expanded to 64 KB, 256 KB, or 1 MB) xxFFFFFFH On-chip peripheral I/O Internal RAM xxFF7FFFH Image Physical external memory xFFFFH Image External memory x0000H Image xx100000H Internal ROM xx000000H 62 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS Figure 3-13. External Memory Area (When Expanded to 4 MB) xxFFFFFFH On-chip peripheral I/O Internal RAM xxFF7FFFH Image xxC00000H xxBFFFFFH xx800000H xx7FFFFFH Physical external memory 3FFFFFH FCAN address area 3FF800H 3FF7FFH External memory Image 000000H xx400000H xx3FFFFFH Image xx100000H xx0FFFFFH Internal ROM xx000000H User's Manual U14665EJ4V0UD 63 CHAPTER 3 CPU FUNCTIONS 3.4.6 External expansion mode The V850/SF1 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set to the external expansion mode by using the memory expansion mode register (MM). Because the V850/SF1 is fixed to single-chip mode in the normal operation mode, the pins related to the bus interface are in the port mode after reset, and therefore the external memory cannot be used. When the external memory is used (external expansion mode), set the MM register by program. (1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to an external memory area of up to 4 MB. However, the external device cannot be connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed). The MM register can be read/written in 8-bit or 1-bit units. However, bits 4 to 7 are fixed to 0. After reset: 00H 7 MM 0 R/W 6 0 5 0 Address: FFFFF04CH 4 0 3 MM3 2 MM2 1 MM1 0 MM0 MM3 0 1 Port mode P95 and P96 operation modes External expansion mode (HLDAK: P95, HLDRQ: P96) MM2 0 0 MM1 0 1 MM0 0 1 Address space - 64 KB expansion mode Port 4 Port 5 Port mode Port 6 Port 9 AD0 to AD7 AD8 to AD15 A16, A17 A18, A19 A20, A21 LBEN, UBEN, R/W, DSTB, ASTB 1 0 0 256 KB expansion mode 1 0 1 1 MB expansion mode 1 1 x 4 MB expansion mode Other than above RFU (reserved) Caution Before switching to the external expansion mode, be sure to set P93 and P94 of Port 9 (P9) to 1. Remark For details of the operation of each port pin, refer to 2.3 Description of Pin Functions. 64 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.4.7 Recommended use of address space The architecture of the V850/SF1 requires that a register that serves as a pointer be secured for address generation in operand data accessing for data space. The address in this pointer register 32 KB can be accessed directly from an instruction. However, the general-purpose registers that can be used as a pointer register are limited. Therefore, by minimizing the deterioration of the address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved because instructions for calculating pointer addresses are not required. To enhance the efficiency of using the pointer in connection with the memory maps of the V850/SF1, the following points are recommended: (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Therefore, a continuous 16 MB space, starting from address 00000000H, unconditionally corresponds to the memory map of the program space. (2) Data space For the efficient use of resources that utilize the wraparound feature of the data space, the continuous 8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space. With the V850/SF1, a 16 MB physical address space is seen as 256 images in the 4 GB CPU address space. The most significant bit (bit 23) of this 24-bit address is assigned as address sign-extended to 32 bits. (a) Application of wraparound For example, when R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, an addressing range of 00000000H 32 KB can be referenced with the sign-extended disp16. All resources including onchip hardware can be accessed with one pointer. The zero register (r0) is a register set to 0 by hardware, and eliminates the need for additional registers for the pointer. Figure 3-14. Application of Wraparound 0007FFFFH 00007FFFH Internal ROM area (R =) 00000000H FFFFF000H On-chip peripheral I/O area Internal RAM area FFFFB000H FFFF8000H Access-prohibited area 12 KB 4 KB 16 KB 32 KB User's Manual U14665EJ4V0UD 65 CHAPTER 3 CPU FUNCTIONS Figure 3-15. Recommended Memory Map (Flash Memory Version) Program space FFFFFFFFH FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH Data space On-chip peripheral I/O Internal RAM FFFF8000H FFFF7FFFH On-chip peripheral I/O xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH External memory FF800000H FF7FFFFFH Internal RAM xxFFB000H Access prohibited xxFFAFFFH xxFF8000H area 01000000H 00FFFFFFH On-chip peripheral I/ONote 1 00FFF000H 00FFEFFFH External memory Note 2 xxFF7FFFH xx800000H xx7FFFFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx000000H Internal RAM 16 MB 00FF8000H 00FF7FFFH Internal ROM External memory 00800000H 007FFFFFH External memory 8 MB 00100000H 000FFFFFH 00040000H 0003FFFFH 00000000H Internal ROM Internal ROM Notes 1. 2. This area cannot be used as a program area. Addresses xxnF800H to xxnFFFFH (n = 3, 7, B) are an FCAN address area and cannot be accessed during external expansion. Remarks 1. The arrows indicate the recommended area. 2. This is a recommended memory map for the PD70F3079AY and 70F3079Y. 66 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/7) Bit Units for Manipulation Address FFFFF000H FFFFF002H FFFFF004H FFFFF006H FFFFF008H FFFFF00AH FFFFF00CH FFFFF00EH FFFFF010H FFFFF012H FFFFF014H FFFFF016H FFFFF020H FFFFF022H FFFFF024H FFFFF026H FFFFF028H FFFFF02AH FFFFF02CH FFFFF032H FFFFF034H FFFFF036H FFFFF040H FFFFF04CH FFFFF060H FFFFF062H FFFFF070H FFFFF074H FFFFF078H Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 0 mode register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 9 mode register Port 10 mode register Port 11 mode register Port alternate function control register Memory expansion mode register Data wait control register Bus cycle control register Power save control register Processor clock control register System status register Function Register Name Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM9 PM10 PM11 PAC MM DWC BCC PSC PCC SYS R/W 1 Bit R/W After Reset 8 Bits 16 Bits 32 Bits 00H Note R Undefined R/W 00H Note FFH 3FH FFH 1FH FFH 3FH 7FH FFH 00H FFFFH AAAAH C0H 03H 00H Note Resetting initializes registers to input mode, so 00H cannot actually be read. User's Manual U14665EJ4V0UD 67 CHAPTER 3 CPU FUNCTIONS (2/7) Bit Units for Manipulation Address FFFFF07AH FFFFF07CH FFFFF094H FFFFF0A2H FFFFF0C0H FFFFF0C2H FFFFF0E4H FFFFF0E6H FFFFF0EAH FFFFF0ECH FFFFF0EEH FFFFF100H FFFFF102H FFFFF104H FFFFF106H FFFFF108H FFFFF10AH FFFFF10CH FFFFF10EH FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH Function Register Name POC status register VM45 control register Pull-up resistor option register 10 Port 1 function register Rising edge specification register 0 Falling edge specification register 0 Timer clock selection register 30 16-bit timer mode control register 30 16-bit counter 3 16-bit compare register 3 Timer clock selection register 31 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Symbol POCS VM45C PU10 PF1 EGP0 EGN0 TCL30 TMC30 TM3 CR3 TLC31 WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIC4 ADIC DMAIC0 DMAIC1 DMAIC2 TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 WTNIC WTNIIC CSIC0 R/W 1 Bit R R/W After Reset 8 Bits 16 Bits 32 Bits Held Note 1 00H 04H Note 2 R R/W 0000H 00H 47H Notes 1. 2. This value is 03H only after a power-on-clear reset. This cannot be reset by RESET signal input or watchdog timer. Although the hardware status is initialized to 04H, 00H is read out if read. 68 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (3/7) Bit Units for Manipulation Address FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF166H FFFFF170H FFFFF180H FFFFF182H FFFFF184H FFFFF186H FFFFF190H FFFFF192H FFFFF194H FFFFF196H FFFFF1A0H FFFFF1A2H FFFFF1A4H FFFFF1A6H FFFFF1B0H FFFFF1B2H Function Register Name Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Note Symbol SERIC0 CSIC1 STIC0 KRIC CANIC1 CANIC2 CANIC3 CANIC7 TMIC6 TMIC70 TMIC71 SERIC1 CSIC3 STIC1 DMAIC3 DMAIC4 DMAIC5 CANIC4 CANIC5 CANIC6 ISPR PRCMD DIOA0 DRA0 DBC0 DCHC0 DIOA1 DRA1 DBC1 DCHC1 DIOA2 DRA2 DBC2 DCHC2 DIOA3 DRA3 R/W 1 Bit R/W After Reset 8 Bits 16 Bits 32 Bits 47H Note Note In-service priority register Command register DMA peripheral I/O address register 0 DMA internal RAM address register 0 DMA byte count register 0 DMA channel control register 0 DMA peripheral I/O address register 1 DMA internal RAM address register 1 DMA byte count register 1 DMA channel control register 1 DMA peripheral I/O address register 2 DMA internal RAM address register 2 DMA byte count register 2 DMA channel control register 2 DMA peripheral I/O address register 3 DMA internal RAM address register 3 R W R/W 00H Undefined 00H Undefined 00H Undefined 00H Undefined Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. User's Manual U14665EJ4V0UD 69 CHAPTER 3 CPU FUNCTIONS (4/7) Bit Units for Manipulation Address FFFFF1B4H FFFFF1B6H FFFFF1C0H FFFFF1C2H FFFFF1C4H FFFFF1C6H FFFFF1D0H FFFFF1D2H FFFFF1D4H FFFFF1D6H FFFFF200H FFFFF202H FFFFF204H FFFFF206H FFFFF208H FFFFF20AH FFFFF20CH FFFFF20EH FFFFF210H FFFFF212H FFFFF214H FFFFF216H FFFFF218H FFFFF21AH FFFFF21CH FFFFF21EH FFFFF244H FFFFF246H FFFFF24AH FFFFF24CH FFFFF24EH Function Register Name DMA byte count register 3 DMA channel control register 3 DMA peripheral I/O address register 4 DMA internal RAM address register 4 DMA byte count register 4 DMA channel control register 4 DMA peripheral I/O address register 5 DMA internal RAM address register 5 DMA byte count register 5 DMA channel control register 5 16-bit timer register 0 Capture/compare register 00 Capture/compare register 01 Prescaler mode register 00 16-bit timer mode control register 0 Capture/compare control register 0 16-bit timer output control register 0 Prescaler mode register 01 16-bit timer register 1 Capture/compare register 10 Capture/compare register 11 Prescaler mode register 10 16-bit timer mode control register 1 Capture/compare control register 1 16-bit timer output control register 1 Prescaler mode register 11 Timer clock select register 20 16-bit timer mode control register 20 16-bit counter 2 16-bit compare register 2 Timer clock selection register 21 Symbol DBC3 DCHC3 DIOA4 DRA4 DBC4 DCHC4 DIOA5 DRA5 DBC5 DCHC5 TM0 CR00 CR01 PRM00 TMC0 CRC0 TOC0 PRM01 TM1 CR10 CR11 PRM10 TMC1 CRC1 TOC1 PRM11 TCL20 TMC20 TM2 CR2 TCL21 R R/W R/W 1 Bit R/W After Reset 8 Bits 16 Bits 32 Bits Undefined 00H Undefined 00H Undefined 00H 0000H R Note Note R/W 00H R Note Note R/W 0000H 00H 04H 0000H 00H Note In compare mode: R/W In capture mode: R 70 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (5/7) Bit Units for Manipulation Address FFFFF264H FFFFF266H FFFFF26AH FFFFF26CH FFFFF26EH FFFFF284H FFFFF286H FFFFF28AH FFFFF28CH FFFFF28EH FFFFF2A0H FFFFF2A2H FFFFF2A4H FFFFF2B0H FFFFF2B2H FFFFF2B4H FFFFF2D0H FFFFF2D2H FFFFF2D4H FFFFF2E0H FFFFF2E2H FFFFF2E4H FFFFF2E6H Function Register Name Timer clock selection register 40 16-bit timer mode control register 40 16-bit counter 4 16-bit compare register 4 Timer clock selection register 41 Timer clock selection register 60 16-bit timer mode control register 60 16-bit counter 6 16-bit compare register 6 Timer clock selection register 61 Serial I/O shift register 0 Serial operation mode register 0 Serial clock selection register 0 Serial I/O shift register 1 Serial operation mode register 1 Serial clock selection register 1 Serial I/O shift register 3 Serial operation mode register 3 Serial clock selection register 3 Variable-length serial I/O shift register 4 Variable-length serial control register 4 Variable-length serial setting register 4 Baud rate generator source clock selection register 4 FFFFF2E8H Baud rate generator output clock selection register 4 FFFFF300H FFFFF302H FFFFF304H FFFFF306H FFFFF308H FFFFF30EH FFFFF310H FFFFF312H FFFFF314H FFFFF316H FFFFF318H Asynchronous serial interface mode register 0 Asynchronous serial interface status register 0 Baud rate generator control register 0 Transmission shift register 0 Reception buffer register 0 Baud rate generator mode control register 00 Asynchronous serial interface mode register 1 Asynchronous serial interface status register 1 Baud rate generator control register 1 Transmission shift register 1 Reception buffer register 1 ASIM0 ASIS0 BRGC0 TXS0 RXB0 R R/W W R Symbol TCL40 TMC40 TM4 CR4 TCL41 TCL60 TMC60 TM6 CR6 TCL61 SIO0 CSIM0 CSIS0 SIO1 CSIM1 CSIS1 SIO3 CSIM3 CSIS3 SIO4 CSIM4 CSIB4 BRGCN4 R/W 1 Bit R/W After Reset 8 Bits 16 Bits 32 Bits 00H 04H Note R R/W 0000H 00H 04H Note R R/W 0000H 00H 0000H 00H BRGCK4 7FH 00H FFH BRGMC00 R/W ASIM1 ASIS1 BRGC1 TXS1 RXB1 R R/W W R 00H FFH Note Although the hardware status is initialized to 04H, 00H is read out if read. User's Manual U14665EJ4V0UD 71 CHAPTER 3 CPU FUNCTIONS (6/7) Bit Units for Manipulation Address FFFFF31EH FFFFF320H FFFFF322H FFFFF334H FFFFF336H FFFFF33AH FFFFF33CH FFFFF33EH FFFFF340H FFFFF342H FFFFF344H FFFFF346H FFFFF348H FFFFF34AH FFFFF34CH FFFFF360H FFFFF364H FFFFF36CH FFFFF36EH FFFFF370H FFFFF374H FFFFF378H FFFFF37CH FFFFF380H FFFFF382H FFFFF384H FFFFF38EH FFFFF3A0H FFFFF3A2H FFFFF3A4H FFFFF3A6H FFFFF3A8H Function Register Name Baud rate generator mode control register 10 Baud rate generator mode control register 01 Baud rate generator mode control register 11 Timer clock selection register 50 16-bit timer mode control register 50 16-bit counter 5 16-bit compare register 5 Timer clock selection register 51 IIC control register 0 IIC state register 0 IIC clock selection register 0 Slave address register 0 IIC shift register 0 IIC function expansion register 0 IIC clock expansion register 0 Watch timer mode control register Watch timer clock selection register Correction control register Correction request register Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Oscillation stabilization time selection register Watchdog timer clock selection register Watchdog timer mode register DMA trigger expansion register 16-bit timer register 7 Capture/compare register 70 Capture/compare register 71 Prescaler mode register 70 16-bit timer mode control register 7 Symbol R/W 1 Bit BRGMC10 R/W BRGMC01 BRGMC11 TCL50 TMC50 TM5 CR5 TCL51 IICC0 IICS0 IICCL0 SVA0 IIC0 IICX0 IICCE0 WTNM WTNCS CORCN CORRQ CORAD0 CORAD1 CORAD2 CORAD3 OSTS WDCS WDTM DMAS TM7 CR70 CR71 PRM70 TMC7 R/W After Reset 8 Bits 16 Bits 32 Bits 00H R R/W 0000H 00H R R/W 00000000H Note 1 00H R Note 2 0000H 00H Notes 1. 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y 2. In compare mode: R/W In capture mode: R 72 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (7/7) Bit Units for Manipulation Address FFFFF3AAH FFFFF3ACH FFFFF3AEH FFFFF3C0H FFFFF3C2H FFFFF3C4H FFFFF3C6H FFFFF3C8H FFFFF3D0H FFFFF3D4H Function Register Name Capture/compare control register 7 16-bit timer output control register 7 Prescaler mode register 71 A/D converter mode register 1 Analog input channel specification register A/D conversion result register A/D conversion result register H (higher 8 bits) A/D converter mode register 2 Key return mode register Noise elimination control register Symbol CRC7 TOC7 PRM71 ADM1 ADS ADCR ADCRH ADM2 KRM NCC R/W R/W 1 Bit R/W After Reset 8 Bits 16 Bits 32 Bits 00H R 0000H 00H User's Manual U14665EJ4V0UD 73 CHAPTER 3 CPU FUNCTIONS 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, the system status register (SYS) is notified. The V850/SF1 has two specific registers, the power save control register (PSC) and processor clock control register (PCC). For details of the PSC register, refer to 4.3.1 (2) Power save control register (PSC), and for details of the PCC register, refer to 4.3.1 (1) Processor clock control register (PCC). The following sequence shows data setting in the specific registers. <1> Disable DMA operation. <2> Set the PSW NP bit to 1 (interrupt disabled). <3> Write any 8-bit data in the command register (PRCMD). <4> Write the set data in the specific registers (by the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Return the PSW NP bit to 0 (interrupt disable canceled). <6> If necessary, enable DMA operation. No special sequence is required when reading the specific registers. Cautions 1. If an interrupt request or a DMA request is acknowledged between the time PRCMD is generated (<3>) and the specific register write operation (<4>) that follows immediately after, the write operation to the specific register is not performed and a protection error (PRERR bit of SYS register = 1) may occur. Therefore, set the NP bit of PSW to 1 (<2>) to disable the acknowledgement of INT/NMI or to disable DMA transfer. The above also applies when a bit manipulation instruction is used to set a specific register. A description example is given below. [Description example]: In case of PCC register LDSR ST.B ST.B LDSR rX.5 r0, PRCMD[r0] rD, PCC[r0] rY, 5 . . . ; NP bit = 1 ; Write to PRCMD ; PCC register setting ; NP bit = 0 Remark The above example assumes that rD (PCC set value), rX (value to be written to PSW), and rY (value rewritten to PSW) are already set. When saving the value of the PSW, the value of the PSW prior to setting the NP bit must be transferred to the rY register. 2. Always stop DMA prior to accessing specific registers. 3. If data is set to the PSC register to set IDLE mode or STOP mode, a dummy instruction needs to be inserted for correct execution of the routine after IDLE or STOP mode is released. For details, refer to 4.6 Cautions on Power Save Function. 74 User's Manual U14665EJ4V0UD CHAPTER 3 CPU FUNCTIONS (1) Command register (PRCMD) The command register (PRCMD) is used to prevent incorrect writing to the specific registers due to an inadvertent program loop when write-accessing the specific register. This register can be written in 8-bit units. It becomes undefined in a read cycle. The occurrence of illegal store operations can be checked by the PRERR bit of the SYS register. After reset: Undefined 7 PRCMD REG7 W 6 REG6 5 REG5 Address: FFFFF170H 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0 REGn 0/1 Any 8-bit data Registration code Remark n = 0 to 7 (2) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read/written in 8-bit or 1-bit units. After reset: 00H 7 SYS 0 R/W 6 0 5 0 Address: FFFFF078H 4 PRERR 3 0 2 0 1 0 0 0 PRERR 0 1 Detection of protection error Protection error did not occur Protection error occurred The operation conditions of PRERR flag are shown below. (a) Set conditions (PRERR = 1) (1) When a write operation to a specific register took place in a state where the store instruction operation for the recent peripheral I/O was not a write operation to the PRCMD register. (2) When the first store instruction operation following a write operation to the PRCMD register is to any peripheral I/O register apart from specific registers. (b) Reset conditions: (PRERR = 0) (1) When 0 is written to the PRERR flag of the SYS register. (2) At system reset. Remarks 1. If 0 is written to the PRERR bit immediately after a write operation to the PRCMD register, the PRERR bit is set to 1 (because the SYS register is not a specific register). 2. If the PRCMD register is written again immediately after a write operation to the PRCMD register, the PRERR bit of the SYS register is set to 1 (because the SYS register is not a specific register). User's Manual U14665EJ4V0UD 75 CHAPTER 4 CLOCK GENERATION FUNCTION 4.1 General The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of system clock oscillators. (1) Main clock oscillator The main clock oscillator of V850/SF1 has an oscillation frequency of 2 to 16 MHz. Oscillation can be stopped by setting the STOP mode or by setting the processor clock control register (PCC). Oscillation is also stopped during a reset. In the IDLE mode, supplying the peripheral clock to the clock timer only is possible. Therefore, in the IDLE mode, it is possible to operate the clock timer without using the subclock oscillator. Cautions 1. When the main clock oscillator is stopped by inputting a reset or setting the STOP mode, oscillation stabilization time is secured after the stop mode is released. This oscillation stabilization time is set via the oscillation stabilization time selection register (OSTS). The watchdog timer is used to count the oscillation stabilization time. 2. If the main clock halt is released by clearing the MCK bit to 0 after the main clock is stopped by setting the MCK bit in the PCC register to 1, the oscillation stabilization time is not secured. (2) Subclock oscillator This circuit has an oscillation frequency of 32.768 kHz. Its oscillation is not stopped when the STOP mode is set, nor when a reset is input. When the subclock oscillator is not used, the FRC bit in the processor clock control register (PCC) can be set to disable use of the internal feedback resistor. This enables the current consumption to be kept low in the STOP mode. 76 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION 4.2 Configuration Figure 4-1. Clock Generator FRC XT1 XT2 Subclock oscillator fXT IDLE X1 X2 Main clock oscillator IDLE control IDLE control Clock supplied to watch timer, etc. CK2 to CK0 fXX Prescaler fXT fXX/2 fXX/4 fXX/8 STP, MCK Selector HALT control HALT CPU clock (fCPU) Prescaler Clock supplied to peripheral hardware CLKOUT 4.3 Clock Output Function This function outputs the CPU clock via the CLKOUT pin. When clock output is enabled, the CPU clock is output via the CLKOUT pin. When it is disabled, a low-level signal is output via the CLKOUT pin. Output is stopped in the IDLE or STOP mode (fixed to low level). This function is controlled via the DCLK1 and DCLK0 bits in the PSC register. A high-impedance status is set during the reset period. After reset is released, a low level is output. Caution While CLKOUT is being output, the CPU clock (CK2 to CK0 bits of PCC register) cannot be changed. User's Manual U14665EJ4V0UD 77 CHAPTER 4 CLOCK GENERATION FUNCTION 4.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in 8-bit or 1-bit units. After reset: 03H 7 R/W 6 MCK Address: FFFFF074H 5 0 4 0 3 0 2 CK2 1 CK1 0 CK0 PCC FRC FRC 0 1 Used Not used Selection of internal feedback resistor for subclock MCK 0 1 Operating Stopped Operation of main clock CK2 Notes 1, 2 CK1 0 0 1 1 X CK0 0 1 0 1 X fXX fXX/2 fXX/4 fXX/8 fXT (subclock) Selection of CPU clock 0 0 0 0 1 Notes 1. It is recommended to manipulate CK2 in 1-bit units. However, when manipulating the PCC register in 8-bit units, be sure not to change the values of CK1 and CK0. 2. Do not set the STOP mode when the CPU is operating on the subclock (CK2 = 1). Cautions 1. Do not change the CPU clock (the value of the CK2 to CK0 in the PCC register) while CLKOUT is being output. 2. Even if the MCK bit is set to 1 during main clock operation, the main clock is not stopped. The CPU clock stops after the subclock is selected. 3. Be sure to set bits 5 to 3 to 0. Remark X: Either 0 or 1 78 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION (a) Example of main clock operation subclock operation setup <1> CK2 1: <2> Subclock operation: Bit manipulation instructions are recommended. Do not change CK1 and CK0. The maximum number of the following instructions is required before subclock operation after the CK2 bit is set. (CPU clock frequency before setting/subclock frequency) x 2 <3> MCK 1: Therefore, insert waits equivalent to this number by program. Only when the main clock is stopped. (b) Example of subclock operation main clock operation setup <1> MCK 0: Main clock oscillation start <2> Insert waits by program and wait until the main clock oscillation stabilization time elapses. <3> CK2 0 <4> Main clock operation: It takes up to two instructions to start main clock operation after the CK2 bit is set. User's Manual U14665EJ4V0UD 79 CHAPTER 4 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8-bit or 1-bit units. After reset: C0H 7 R/W 6 DCLK0 Address: FFFFF070H 5 0 4 0 3 0 2 IDLE 1 STP 0 0 PSC DCLK1 DCLK1 0 0 1 1 DCLK0 0 1 0 1 Output enabled Note 1 Setting prohibited Specification of CLKOUT pin operation Output disabled (low-level output) IDLE 0 1 Normal mode IDLE mode Note 2 IDLE mode setting STP 0 1 Normal mode STOP mode Note 3 STOP mode setting Notes 1. * PD703078Y, 703079Y, 70F3079Y: Setting prohibited * PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY: Hi-Z output Hi-Z cannot be output from the in-circuit emulator. 2. 3. Caution When IDLE mode is released, this bit is automatically reset to 0. When STOP mode is released, this bit is automatically reset to 0. The bits in DCLK0 and DCLK1 should be manipulated in 8-bit units. 80 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION (3) Oscillation stabilization time selection register (OSTS) This register can be read/written in 8-bit units. After reset: Note 7 R/W 6 0 Address: FFFFF380H 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS 0 OSTS2 OSTS1 OSTS0 Clock Selection of oscillation stabilization time fXX 16 MHz 8 MHz 8.19 ms 32.8 ms 65.5 ms 131 ms 262 ms 0 0 0 0 1 Other than above 0 0 1 1 0 0 1 0 1 0 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX Setting prohibited 21 20 19 18 16 4.10 ms 16.4 ms 32.8 ms 65.5 ms 131 ms Note 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y User's Manual U14665EJ4V0UD 81 CHAPTER 4 CLOCK GENERATION FUNCTION 4.4 Power Save Functions 4.4.1 General This product provides the following power save functions. These modes can be combined and switched to suit the target application, thus enabling the effective implementation of low-power systems. (1) HALT mode In this mode, the clock oscillator continues to operate but the CPU operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. This enables the system's total power consumption to be reduced. A dedicated instruction (the HALT instruction) is used to switch to HALT mode. (2) IDLE mode This mode stops the entire system by stopping the CPU operating clock as well as the operating clock for on-chip peripheral functions while the clock oscillator is still operating. However, the subclock continues to operate and supplies a clock to the on-chip peripheral functions. When this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. When the IDLE bit in the power saving control register (PSC) is set (1), the system switches to IDLE mode. (3) Software STOP mode This mode stops the entire system by stopping the clock oscillator for the main clock. The subclock continues to be supplied to keep on-chip peripheral functions operating. subclock. If the STP bit of the PSC register is set (1), the system enters STOP mode. (4) Subclock operation In this mode, the CPU clock is set to operate using the subclock and the MCK bit of the PCC register is set (1) to set low-power-consumption mode in which the entire system operates using only the subclock. When HALT mode has been set, the CPU operating clock is stopped so that power consumption can be reduced. When IDLE mode has been set, the CPU operating clock and some peripheral functions (DMAC and BCU) are stopped to enable an even greater reduction in power consumption than when in HALT mode. If the subclock is not used, ultra-low-powerconsumption mode (leakage current only) is set. STOP mode setting is prohibited if the CPU is operating via the 82 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.2 HALT mode (1) Settings and operating states In this mode, the clock oscillator continues to operate but the CPU operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When HALT mode is set while the CPU is idle, it enables the system's total power consumption to be reduced. When in HALT mode, execution of programs is stopped but the contents of all registers and on-chip RAM are retained as they were just before HALT mode was set. In addition, all on-chip peripheral functions that do not depend on instruction processing by the CPU continue operating. HALT mode can be set by executing the HALT instruction. It can be set when the CPU is operating via either the main clock or subclock. The operating statuses in the HALT mode are listed in Table 4-1. (2) Release of HALT mode HALT mode can be released by an NMI request, an unmasked maskable interrupt request, or RESET input. (a) Release by interrupt request HALT mode is released regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs. servicing routine. (i) When an interrupt request that has a lower priority level than the interrupt currently being serviced occurs, only HALT mode is released and the lower-priority interrupt request is not acknowledged. The interrupt request itself is retained. (ii) When an interrupt request (including NMI request) that has a higher priority level than the interrupt currently being serviced occurs, HALT mode is released and the interrupt request is acknowledged. (b) Release by RESET pin input This is the same as for normal reset operations. However, the following occurs if HALT mode was set as part of an interrupt User's Manual U14665EJ4V0UD 83 CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When CPU Operates on Main Clock When Subclock Does Item CPU ROM correction Clock generator Not Exist Stopped Stopped Oscillation for main clock and subclock Clock supply to CPU is stopped 16-bit timer (TM0) Operating Operates when INTWTNI is selected as count clock (fXT is selected for watch timer) 16-bit timer (TM1) 16-bit timer (TM2) 16-bit timer (TM3) 16-bit timer (TM4) Operating Operating Operating Operates when other than fXT is selected as count clock 16-bit timer (TM5) Operates when other than fXT is selected as count clock 16-bit timer (TM6) 16-bit timer (TM7) Watch timer Operating Operating Operates when main clock is selected as count clock Watchdog timer Serial interface CSI0, CSI1, CSI3 I C0 UART0, UART1 2 When CPU Operates on Subclock When Main Clock Oscillation Continues When Main Clock Oscillation Is Stopped When Subclock Exists Stopped Stopped Stopped Operating Operates when fXT is selected as count clock Operating Operates when fXT is selected as count clock Stopped Stopped Operating Operates when fXT is selected as count clock Operating (interval timer only) Operating Operates when external clock is selected as serial clock Operating Operating Stopped Operates when external clock is selected as baud rate clock CSI4 Operating Operates when external clock is selected as serial clock FCAN1, FCAN2 A/D converter DMA0 to DMA5 Note Operating Operating Operating Stopped Stopped Note Available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. 84 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When CPU Operates on Main Clock When Subclock Does Item Port function External bus interface External interrupt requests NMI INTP0 to INTP3 INTP4 and INTP5 INTP6 Not Exist Held Only bus hold function operates Operating Operating Operating Operates when other than fXT is selected for noise eliminator Key return function In external expansion mode AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB ASTB HLDAK Operating Operating High impedance Held Held Note Note When CPU Operates on Subclock When Main Clock Oscillation Continues When Main Clock Oscillation Is Stopped When Subclock Exists Stopped Operating Operates when fXT is selected for noise eliminator (high impedance when HLDAK = 0) (high impedance when HLDAK = 0) Note Note High level output (high impedance when HLDAK = 0) Note Even when the HALT instruction has been executed, the instruction fetch operation continues until the on-chip instruction prefetch queue becomes full. Once it is full, operation stops in the state shown in Table 4-1. User's Manual U14665EJ4V0UD 85 CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply of the subclock continues. When this mode is released, there is no need for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly. When in IDLE mode, program execution is stopped and the contents of all registers and internal RAM are retained as they were just before IDLE mode was set. In addition, on-chip peripheral functions are stopped (except for peripheral functions that are operating with the subclock). acknowledged. When the IDLE bit of the power save control register (PSC) is set (1), the system switches to IDLE mode. The operating statuses in IDLE mode are listed in Table 4-2. (2) Release of IDLE mode IDLE mode can be released by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral I/O, or RESET input. Table 4-2. Operating Statuses in IDLE Mode (1/2) IDLE Mode Settings Item CPU ROM correction Clock generator 16-bit timer (TM0) 16-bit timer (TM1) 16-bit timer (TM2) 16-bit timer (TM3) 16-bit timer (TM4) 16-bit timer (TM5) 16-bit timer (TM6) 16-bit timer (TM7) Watch timer Watchdog timer Serial interface CSI0, CSI1, CSI3 I C0 UART0, UART1 CSI4 FCAN1, FCAN2 A/D converter DMA0 to DMA5 Port function Note 2 External bus hold requests (HLDRQ) are not When Subclock Exists When Subclock Does Not Exist Stopped Stopped Both main clock and subclock oscillating Clock supply to CPU and on-chip peripheral functions is stopped Operates when INTWTNI is selected as count clock (fXT is selected for watch timer) Stopped Stopped Stopped Operates when fXT is selected as count clock Operates when fXT is selected as count clock Stopped Stopped Operating Stopped Operates when external clock is selected as serial clock Stopped Operates only for transmission when external clock is selected as baud rate clock Operates when external clock is selected as serial clock Stopped Stopped Stopped Held Stopped Stopped Stopped Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. 86 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings Item External bus interface External interrupt requests NMI INTP0 to INTP3 INTP4 and INTP5 INTP6 Key return function In external expansion mode AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB ASTB HLDAK Stopped Operating Operating Stopped Operates when fXT is selected as sampling clock Operating High impedance Stopped When Subclock Exists When Subclock Does Not Exist User's Manual U14665EJ4V0UD 87 CHAPTER 4 CLOCK GENERATION FUNCTION 4.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator supplying the internal main clock. The subclock oscillator continues operating and the internal subclock supply is continued. If the FRC bit in the processor clock control register (PCC) is set (1) when the subclock oscillator is used, the subclock oscillator's on-chip feedback resistor is cut. This sets ultra-low-power-consumption mode, in which the only current is the device's leakage current. In this mode, program execution is stopped and the contents of all registers and internal RAM are retained as they were just before software STOP mode was set. On-chip peripheral functions are also stopped (but peripheral functions operating on the subclock are not stopped). acknowledged. This mode can be set only when the main clock is being used as the CPU clock. This mode is set when the STP bit in the power save control register (PSC) has been set to 1. Do not set this mode when the subclock has been selected as the CPU clock. The operating statuses for software STOP mode are listed in Table 4-3. Caution In order to reduce the current consumption in software STOP mode, be sure to initialize the FCAN settings as described below, regardless of the use of FCAN. <1> Set the GOM bit of the CGST register to "1" (set GOM = 1, clear GOM = 0) <2> Set the SMNO1 and SMNO0 bits of the CGMSS register to "01" <3> Set the GOM bit of the CGST register to "0" (set GOM = 0, clear GOM = 1) For details of FCAN settings, refer to CHAPTER 18 FCAN CONTROLLER. (2) Release of software STOP mode Software STOP mode can be released by a non-maskable interrupt, an unmasked maskable interrupt request output from an operable on-chip peripheral I/O, or RESET input. When the STOP mode is released, oscillation stabilization time must be secured. The external bus hold request (HLDRQ) is not 88 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION Table 4-3. Operating Statuses in Software STOP Mode STOP Mode Settings When Subclock Exists When Subclock Does Not Exist Item CPU ROM correction Clock generator 16-bit timer (TM0) 16-bit timer (TM1) 16-bit timer (TM2) 16-bit timer (TM3) 16-bit timer (TM4) 16-bit timer (TM5) 16-bit timer (TM6) 16-bit timer (TM7) Watch timer Watchdog timer Serial interface CSI0, CSI1, CSI3 I C0 UART0, UART1 CSI4 FCAN1, FCAN2 A/D converter DMA0 to DMA5 Port function External bus interface External interrupt requests NMI INTP0 to INTP3 INTP4 and INTP5 INTP6 Key return function In external expansion mode AD0 to AD15 A16 to A21 LBEN, UBEN R/W DSTB ASTB HLDAK Note 2 Stopped Stopped Oscillation for main clock is stopped and oscillation for subclock continues Clock supply to CPU and on-chip peripheral functions is stopped Operates when INTWTNI is selected as count clock (fXT is selected as count clock for watch timer) Stopped Stopped Stopped Operates when fXT is selected as count clock Operates when fXT is selected as count clock Stopped Stopped Operates when fXT is selected as count clock Stopped Operates when external clock is selected as serial clock Stopped Operates only for transmission when external clock is selected as baud rate clock Operates when external clock is selected as serial clock Stopped Stopped Stopped Held Stopped Operating Operating Stopped Operates when fXT is selected as sampling clock Operating High impedance Stopped Stopped (operation disabled) Stopped Stopped Stopped Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. User's Manual U14665EJ4V0UD 89 CHAPTER 4 CLOCK GENERATION FUNCTION 4.5 Oscillation Stabilization Time The following shows the methods for specifying the length of oscillation stabilization time required to stabilize the oscillator following release of STOP mode. (1) Release by non-maskable interrupt or by unmasked maskable interrupt request STOP mode is released by a non-maskable interrupt or an unmasked maskable interrupt request. When an interrupt is input, the counter (watchdog timer) starts counting and the count time is the length of time that must elapse until the oscillator's clock output stabilizes. The oscillation stabilization time is set by the oscillation stabilization time selection register (OSTS). * Oscillation stabilization time =* WDT count time After the specified amount of time has elapsed, system clock output starts and processing branches to the interrupt handler address. Figure 4-2. Oscillation Stabilization Time STOP mode is set Oscillation wave Main clock STOP status Interrupt input Oscillator is stopped Oscillation stabilization time count (2) Use of RESET pin to secure time (RESET pin input) For securing time using the RESET pin, refer to CHAPTER 14 RESET FUNCTION. The oscillation stabilization time is as follows in accordance with the value of the OSTS register after reset, which differs depending on the device. 218/fXX: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 221/fXX: PD703078Y, 703079Y, 70F3078AY 90 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION 4.6 Cautions on Power Save Function (1) When executing an instruction on the internal ROM To set the power save mode (IDLE or STOP mode) during execution of an instruction on the internal ROM, NOP instructions must be inserted as dummy instructions to execute the routine after the power save mode is released. The sequence for setting the power save mode is as follows. <1> Disable DMA operation. <2> Disable interrupts (set NP bit of PSW to 1). <3> Write an arbitrary 8-bit data to the command register (PRCMD). <4> Write the setting data to the PSC register (using the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Enable interrupts (clear NP bit of PSW to 0). <6> Insert NOP instructions (two or five instructions). <7> If DMA operation is needed, enable DMA operation. Cautions 1. Insert two NOP instructions if the value of the ID bit of the PSW is not changed by executing the instruction that clears the NP bit to 0 (<5>), and if changed, insert five NOP instructions (<6>). The following shows an example of description. [Description example] LDSR ST.B ST.B LDSR NOP NOP (next instruction) ... ;execution routine after IDLE/STOP mode released ... rX,5 r0,PRCMD[r0] rD,PSC[r0] rY,5 ;NP bit = 1 ;write to PRCMD ;set PSC register ;NP bit = 0 ;Dummy instructions(2 or 5 instructions) Remark The above example assumes that rD (PSC set value), rX (value to be written to PSW), and rY (value rewritten to PSW) are already set. To save the PSW value, transfer the PSW value before setting the NP bit to the rY register. 2. The instructions (<5> enable interrupt, <6> NOP instruction) following the store instruction (<4>) for the PSC register that is used to set IDLE mode or STOP mode are executed before the power save mode is entered. User's Manual U14665EJ4V0UD 91 CHAPTER 4 CLOCK GENERATION FUNCTION (2) When executing an instruction on the external ROM If the V850/SF1 is used under the following conditions, a discrepancy occurs between the address indicated by the program counter (PC) and the address at which an instruction is actually read after the power save mode is released. This may result in the CPU ignoring a 4- or 8-byte instruction from between 4 bytes and 16 bytes after an instruction is executed to write to the PSC register, which could in turn result in the execution of an erroneous instruction. Caution A PC discrepancy occurs only when all the conditions (i) to (iii) in [Conditions] below are met. It does not occur if even one condition is not met. [Conditions] (i) (ii) Setting of power save mode (IDLE mode or STOP mode) while an instruction is being executed on external ROM Release of power save mode as the result of an interrupt request save mode Conditions for interrupt request to be held pending: * When NP flag of PSW register is "1" (NMI servicing in progress/set by software) * When ID flag of PSW register is "1" (interrupt request servicing in progress/DI instruction/set by software) * When an interrupt enable (EI) state occurs during interrupt request servicing, but this state is cleared by an interrupt request with the same or lower priority Therefore, use the V850/SF1 under the following conditions. [Usage Conditions] (i) (ii) Do not use a power save mode (IDLE mode or STOP mode) during instruction execution on external ROM. If it is necessary to use a power save mode during instruction execution on external ROM, implement the following software measures. * Insert 6 NOP instructions 4 bytes after an instruction that writes to the PSC register. * After the NOP instructions, insert a BR$+2 instruction to cancel the PC discrepancy. (iii) Execution of the next instruction when an interrupt request is held pending following release of the power 92 User's Manual U14665EJ4V0UD CHAPTER 4 CLOCK GENERATION FUNCTION [Workaround program example] LDSR ST.B ST.B LDSR NOP NOP NOP NOP NOP NOP BR rX,5 r0,PRCMD[r0] rD,PSC[r0] rY,5 ;Sets rX value to PSW ;Writes to PRCMD ;Sets PSC register ;Returns PSW value ;6 or more NOP instructions $+2 ;Cancels PC discrepancy It is assumed that rD (PSC setting value), rX (value written to PSW), and rY (value written back to PSW) have been set. Remark User's Manual U14665EJ4V0UD 93 CHAPTER 5 PORT FUNCTION 5.1 Port Configuration The V850/SF1 includes 84 port pins from ports 0 to 11, of which 72 are I/O pins and 12 are input only pins. There are three pin I/O buffer power supplies: ADCVDD, PORTVDD, and VDD0, which are described below. Table 5-1. Pin I/O Buffer Power Supplies Power Supply ADCVDD PORTVDD P70 to P77, P80 to P83 P01 to P07, P10 to P15, P20 to P27, P30 to P34, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P100 to P107, P110 to P117 VDD0 P00, RESET, CLKOUT Corresponding Pins 5.2 Port Pin Functions 5.2.1 Port 0 Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. When using P00 to P04 as the NMI or INTP0 to INTP3 pins, noise is eliminated by an analog noise eliminator. When using P05 to P07 as the INTP4/ADTRG, INTP5, and INTP6 pins, noise is eliminated by a digital noise eliminator. After reset: 00H 7 R/W 6 P06 5 P05 Address: FFFFF000H 4 P04 3 P03 2 P02 1 P01 0 P00 P0 P07 P0n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 7) Remark In input mode: In output mode: When the P0 register is read, the pin levels at that time are read. Writing to P0 writes the values to that register. This does not affect the input pins. When the P0 register is read, the values of P0 are read. Writing to P0 writes the values to that register, and those values are immediately output. 94 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION Port 0 includes the following alternate functions. Table 5-2. Port 0 Alternate-Function Pins Pin Name Port 0 P00 P01 P02 P03 P04 P05 P06 P07 NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5 INTP6 Digital noise elimination Alternate Function I/O I/O PULL No Note Remark Analog noise elimination Note Software pull-up function (1) Function of P0 pins Port 0 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 0 mode register (PM0). In output mode, the values set to each bit are output to port 0 (P0). When using this port in output mode, either the valid edge of each interrupt request should be made invalid or each interrupt request should be masked (except for NMI requests). When using this port in input mode, the pin statuses can be read by reading P0. Also, the values of P0 (output latch) can be read by reading P0 while in output mode. The valid edges of NMI and INTP0 to INTP6 are specified via rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0). When a reset is input, the settings are initialized to input mode. Also, the valid edge of each interrupt request becomes invalid (NMI and INTP0 to INTP6 do not function immediately after reset). (2) Noise elimination (a) Elimination of noise from NMI and INTP0 to INTP3 pins An on-chip noise eliminator is provided that uses analog delay to eliminate noise. Consequently, if a signal having a constant level is input for longer than a specified time to these pins, it is detected as a valid edge. Such edge detection occurs only after the specified amount of time. (b) Elimination of noise from INTP4 to INTP6 and ADTRG pins A digital noise eliminator is provided on chip. This circuit uses digital sampling. A pin's input level is detected using a sampling clock (fxx), and noise elimination is performed for the INTP4, INTP5, and ADTRG pins if the same level is not detected three times consecutively. The noise-elimination width can be changed for the INTP6 pin (see 7.3.8 (3) Noise elimination of INTP6 pin). User's Manual U14665EJ4V0UD 95 CHAPTER 5 PORT FUNCTION Cautions 1. If the input pulse width is 2 to 3 clocks, whether it will be detected as a valid edge or eliminated as noise is undefined. To ensure correct detection of the valid edge, constant-level input is required for 3 clocks or more. 2. If noise is occurring in synchronization with the sampling clock, it may not be recognized as noise. In such cases, attach a filter to the input pins to eliminate the noise. 3. Noise elimination is not performed when these pins are used as an ordinary input port. (3) Control registers (a) Port 0 mode register (PM0) PM0 can be read/written in 8-bit or 1-bit units. After reset: FFH 7 R/W 6 PM06 5 PM05 Address: FFFFF020H 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 PM0 PM07 PM0n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) (b) Rising edge specification register 0 (EGP0) EGP0 can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 EGP06 5 EGP05 Address: FFFFF0C0H 4 EGP04 3 EGP03 2 EGP02 1 EGP01 0 EGP00 EGP0 EGP07 EGP0n 0 1 Control of rising edge detection (n = 0 to 7) Interrupt request signal did not occur at rising edge Interrupt request signal occurred at rising edge Remark n = 0: Control of NMI pin n = 1 to 7: Control of INTP0 to INTP6 pins 96 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (c) Falling edge specification register 0 (EGN0) EGN0 can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 EGN06 5 EGN05 Address: FFFFF0C2H 4 EGN04 3 EGN03 2 EGN02 1 EGN01 0 EGN00 EGN0 EGN07 EGN0n 0 1 Control of falling edge detection (n = 0 to 7) Interrupt request signal did not occur at falling edge Interrupt request signal occurred at falling edge Remark n = 0: Control of NMI pin n = 1 to 7: Control of INTP0 to INTP6 pins (4) Block diagram (Port 0) Figure 5-1. Block Diagram of P00 to P07 RD Selector WRPORT P00/NMI P01/INTP0 P02/INTP1 P03/INTP2 P04/INTP3 P05/INTP4/ADTRG P06/INTP5 P07/INTP6 Internal bus Output latch (P0n) WRPM PM0 PM0n Remarks 1. PM0: Port 0 mode register RD: WR: Port 0 read signal Port 0 write signal 2. n = 0 to 7 User's Manual U14665EJ4V0UD 97 CHAPTER 5 PORT FUNCTION 5.2.2 Port 1 Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Bits 0 and 2 are selectable as normal outputs or N-ch open-drain outputs. After reset: 00H 7 R/W 6 0 5 P15 Address: FFFFF002H 4 P14 3 P13 2 P12 1 P11 0 P10 P1 0 P1n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 5) Remark In input mode: In output mode: When P1 is read, the pin levels at that time are read. Writing to P1 writes the values to that register. This does not affect the input pins. When P1 is read, the values of P1 are read. Writing to P1 writes the values to that register, and those values are immediately output. Port 1 includes the following alternate functions. Table 5-3. Port 1 Alternate-Function Pins Pin Name Port 1 P10 P11 P12 P13 P14 P15 Alternate Function SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 I/O I/O PULL No Note Remark Selectable as N-ch open-drain output - Selectable as N-ch open-drain output - Note Software pull-up function 98 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (1) Function of P1 pins Port 1 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 1 mode register (PM1). In output mode, the values set to each bit are output to port 1 (P1). The port 1 function register (PF1) can be used to specify whether P10 and P12 are normal outputs or N-ch open-drain outputs. When using this port in input mode, the pin statuses can be read by reading P1. Also, the values of P1 (output latch) can be read by reading P1 while in output mode. Clear P1 and the PM1 register to 0 when using alternate-function pins as outputs. The logical sum (ORed result) of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 1 mode register (PM1) PM1 can be read/written in 8-bit or 1-bit units. After reset: 3FH 7 R/W 6 0 5 PM15 Address: FFFFF022H 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1 0 PM1n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) (b) Port 1 function register (PF1) PF1 can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 0 5 0 Address: FFFFF0A2H 4 0 3 0 2 PF12 1 0 0 PF10 PF1 0 PF1n 0 1 Normal output Control of normal output/N-ch open-drain output (n = 0, 2) N-ch open-drain output User's Manual U14665EJ4V0UD 99 CHAPTER 5 PORT FUNCTION (3) Block diagram (Port 1) Figure 5-2. Block Diagram of P10 and P12 RD Selector Internal bus WRPF PF1 PF1n VDD WRPORT Output latch (P1n) WRPM PM1 PM1n P-ch N-ch P10/SI0/SDA0 P12/SCK0/SCL0 Alternate function Remarks 1. PF1: Port 1 function register PM1: Port 1 mode register RD: Port 1 read signal WR: Port 1 write signal 2. n = 0, 2 100 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION Figure 5-3. Block Diagram of P11 and P13 to P15 RD Selector Internal bus WRPORT Output latch (P1n) P11/SO0 P13/SI1/RXD0 P14/SO1/TXD0 P15/SCK1/ASCK0 WRPM PM1 PM1n Alternate function Remarks 1. PM1: Port 1 mode register RD: Port 1 read signal WR: Port 1 write signal 2. n = 1, 3 to 5 User's Manual U14665EJ4V0UD 101 CHAPTER 5 PORT FUNCTION 5.2.3 Port 2 Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: 00H 7 R/W 6 P26 5 P25 Address: FFFFF004H 4 P24 3 P23 2 P22 1 P21 0 P20 P2 P27 P2n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 7) Remark In input mode: In output mode: When P2 is read, the pin levels at that time are read. Writing to P2 writes the values to that register. This does not affect the input pins. When P2 is read, the values of P2 are read. Writing to P2 writes the values to that register, and those values are immediately output. Port 2 includes the following alternate functions. Table 5-4. Port 2 Alternate-Function Pins Pin Name Port 2 P20 P21 P22 P23 P24 P25 P26 P27 Alternate Function SI3/RXD1 SO3/TXD1 SCK3/ASCK1 SI4 SO4 SCK4 - - I/O I/O PULL No Note Remark - Note Software pull-up function 102 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (1) Function of P2 pins Port 2 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 2 mode register (PM2). In output mode, the values set to each bit are output to port 2 (P2). When using this port in input mode, the pin statuses can be read by reading P2. Also, the values of P2 (output latch) can be read by reading P2 while in output mode. Clear P2 and the PM2 register to 0 when using alternate-function pins as outputs. The logical sum (ORed result) of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control register (a) Port 2 mode register (PM2) PM2 can be read/written in 8-bit or 1-bit units. After reset: FFH 7 R/W 6 PM26 5 PM25 Address: FFFFF024H 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 PM2 PM27 PM2n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) User's Manual U14665EJ4V0UD 103 CHAPTER 5 PORT FUNCTION Figure 5-4. Block Diagram of P20 to P25 RD Selector WRPORT Output latch (P2n) P20/SI3/RXD1 P21/SO3/TXD1 P22/SCK3/ASCK1 P23/SI4 P24/SO4 P25/SCK4 Internal bus WRPM PM2 PM2n Alternate function Remarks 1. PM2: Port 2 mode register RD: Port 2 read signal WR: Port 2 write signal 2. n = 0 to 5 Figure 5-5. Block Diagram of P26 and P27 RD Selector Internal bus WRPORT Output latch (P2n) P26, P27 WRPM PM2 PM2n Remarks 1. PM2: Port 2 mode register RD: Port 2 read signal WR: Port 2 write signal 2. n = 6, 7 104 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.2.4 Port 3 Port 3 is a 5-bit I/O port for which I/O settings can be controlled in 1-bit units. When using P30 to P33 as the TI2 to TI5 pins, noise is eliminated by a digital eliminator. After reset: 00H 7 R/W 6 0 5 0 Address: FFFFF006H 4 P34 3 P33 2 P32 1 P31 0 P30 P3 0 P3n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 4) Remark In input mode: In output mode: When P3 is read, the pin levels at that time are read. Writing to P3 writes the values to that register. This does not affect the input pins. When P3 is read, the values of P3 are read. Writing to P3 writes the values to that register, and those values are immediately output. Port 3 includes the following alternate functions. Table 5-5. Port 3 Alternate-Function Pins Pin Name Port 3 P30 P31 P32 P33 P34 Alternate Function TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 VM45/TI71 - I/O I/O PULL No Note Remark Digital noise elimination Note Software pull-up function User's Manual U14665EJ4V0UD 105 CHAPTER 5 PORT FUNCTION (1) Function of P3 pins Port 3 is a 5-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 3 mode register (PM3). In output mode, the values set to each bit are output to port 3 (P3). When using this port in input mode, the pin statuses can be read by reading P3. Also, the values of P3 (output latch) can be read by reading P3 while in output mode. When using the alternate function as TI2 to TI5 pins, noise is eliminated by the digital noise eliminator (same as the digital noise eliminator for port 0). Clear P3 and the PM3 register to 0 when using alternate-function pins as outputs. The logical sum (ORed result) of the port output and the alternate-function pin is output from the pins. When using the alternate-function VM45 pin, set this port via the VM45 control register (VM45C). In this case, be sure to set P34 and PM34 to 0. When a reset is input, the settings are initialized to input mode. (2) Control register (a) Port 3 mode register (PM3) PM3 can be read/written in 8-bit or 1-bit units. After reset: 1FH 7 R/W 6 0 5 0 Address: FFFFF026H 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 PM3 0 PM3n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 4) 106 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (3) Block diagram (Port 3) Figure 5-6. Block Diagram of P30 to P34 RD Selector WRPORT Output latch (P3n) P30/TI2/TO2 P31/TI3/TO3 P32/TI4/TO4 P33/TI5/TO5 P34/VM45/TI71 Internal bus WRPM PM3 PM3n Alternate function Remarks 1. PM3: Port 3 mode register RD: Port 3 read signal WR: Port 3 write signal 2. n = 0 to 4 User's Manual U14665EJ4V0UD 107 CHAPTER 5 PORT FUNCTION 5.2.5 Ports 4 and 5 Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. After reset: 00H 7 R/W 6 Pn6 5 Pn5 Address: FFFFF008H, FFFFF00AH 4 Pn4 3 Pn3 2 Pn2 1 Pn1 0 Pn0 Pn (n = 4, 5) Pn7 Pnx 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 4, 5, x = 0 to 7) Remark In input mode: When P4 and P5 are read, the pin levels at that time are read. Writing to P4 and P5 writes the values to those registers. This does not affect the input pins. In output mode: When P4 and P5 are read, their values are read. Writing to P4 and P5 writes the values to those registers, and those values are immediately output. Ports 4 and 5 include the following alternate functions. Table 5-6. Alternate-Function Pins of Ports 4 and 5 Pin Name Port 4 P40 P41 P42 P43 P44 P45 P46 P47 Port 5 P50 P51 P52 P53 P54 P55 P56 P57 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 I/O No - Alternate Function I/O I/O PULL No Note Remark - Note Software pull-up function 108 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (1) Functions of P4 and P5 pins Ports 4 and 5 are 8-bit I/O ports for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via port 4 mode register (PM4) and port 5 mode register (PM5). In output mode, the values set to each bit are output to the port 4 and port 5 (P4 and P5). When using these ports in input mode, the pin statuses can be read by reading P4 and P5. Also, the values of P4 and P5 (output latch) can be read by reading P4 and P5 while in output mode. A software pull-up function is not implemented. When using the P4 and P5 pins as AD0 to AD15, set the pin functions via the memory expansion mode register (MM). This does not affect the PM4 and PM5 registers. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 4 mode register and port 5 mode register (PM4 and PM5) PM4 and PM5 can be read/written in 8-bit or 1-bit units. After reset: FFH 7 R/W 6 PMn6 5 PMn5 Address: FFFFF028H, FFFFF02AH 4 PMn4 3 PMn3 2 PMn2 1 PMn1 0 PMn0 PMn (n = 4, 5) PMn7 PMnx 0 1 Output mode Input mode Control of I/O mode (n = 4, 5, x = 0 to 7) User's Manual U14665EJ4V0UD 109 CHAPTER 5 PORT FUNCTION (3) Block diagram (Ports 4 and 5) Figure 5-7. Block Diagram of P40 to P47 and P50 to P57 RD Selector Internal bus WRPORT Output latch (Pmn) Pmn/ADx WRPM PMm PMmn Remarks 1. PMm: RD: WR: 2. m = 4, 5 Port m mode register Port m read signal Port m write signal n = 0 to 7 x = 0 to 15 110 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.2.6 Port 6 Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: 00H 7 R/W 6 0 5 P65 Address: FFFFF00CH 4 P64 3 P63 2 P62 1 P61 0 P60 P6 0 P6n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 5) Remark In input mode: In output mode: When P6 is read, the pin levels at that time are read. Writing to P6 writes the values to that register. This does not affect the input pins. When P6 is read, the values of P6 are read. Writing to P6 writes the values to that register, and those values are immediately output. Port 6 includes the following alternate functions. Table 5-7. Port 6 Alternate-Function Pins Pin Name Port 6 P60 P61 P62 P63 P64 P65 A16 A17 A18 A19 A20 A21 Alternate Function I/O I/O PULL No Note Remark - Note Software pull-up function (1) Function of P6 pins Port 6 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 6 mode register (PM6). In output mode, the values set to each bit are output to port 6 (P6). When using this port in input mode, the pin statuses can be read by reading P6. Also, the values of P6 (output latch) can be read by reading P6 while in output mode. A software pull-up function is not implemented. When using the alternate function as A16 to A21, set the pin functions via the memory expansion mode register (MM). This does not affect the PM6 register. When a reset is input, the settings are initialized to input mode. User's Manual U14665EJ4V0UD 111 CHAPTER 5 PORT FUNCTION (2) Control register (a) Port 6 mode register (PM6) PM6 can be read/written in 8-bit or 1-bit units. After reset: 3FH 7 R/W 6 0 5 PM65 Address: FFFFF02CH 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60 PM6 0 PM6n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) (3) Block diagram (Port 6) Figure 5-8. Block Diagram of P60 to P65 RD Selector Internal bus WRPORT Output latch (P6n) P6n/Ax WRPM PM6 PM6n Remarks 1. PM6: Port 6 mode register RD: WR: Port 6 read signal Port 6 write signal 2. n = 0 to 5 x = 16 to 21 112 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.2.7 Ports 7 and 8 Port 7 is an 8-bit input port and port 8 is a 4-bit input port. Both ports are read-only and are accessible in 8-bit or 1bit units. After reset: Undefined 7 R 6 P76 5 P75 Address: FFFFF00EH 4 P74 3 P73 2 P72 1 P71 0 P70 P7 P77 P7n 0/1 Read pin level of bit n Pin level (n = 0 to 7) After reset: Undefined 7 R 6 0 5 0 Address: FFFFF010H 4 0 3 P83 2 P82 1 P81 0 P80 P8 0 P8n 0/1 Read pin level of bit n Pin level (n = 0 to 3) Ports 7 and 8 include the following alternate functions. Table 5-8. Alternate-Function Pins of Ports 7 and 8 Pin Name Port 7 P70 P71 P72 P73 P74 P75 P76 P77 Port 8 P80 P81 P82 P83 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 Input No - Alternate Function I/O Input PULL No Note Remark - Note Software pull-up function User's Manual U14665EJ4V0UD 113 CHAPTER 5 PORT FUNCTION (1) Functions of P7 and P8 pins Port 7 is an 8-bit input-only port and port 8 is a 4-bit input-only port. The pin statuses can be read by reading port 7 and port 8 (P7 and P8). Data cannot be written to P7 or P8. A software pull-up function is not implemented. Values read from pins specified as analog inputs are undefined values. Do not read values from P7 or P8 during A/D conversion. (2) Block diagram (Ports 7 and 8) Figure 5-9. Block Diagram of P70 to P77 and P80 to P83 RD Internal bus Pmn/ANIx Remarks 1. RD: Port 7, port 8 read signals 2. m = 7, 8 n = 0 to 7 (m = 7), 0 to 3 (m = 8) x = 0 to 7 (m = 7), 8 to 11 (m = 8) 114 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.2.8 Port 9 Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. After reset: 00H 7 R/W 6 P96 5 P95 Address: FFFFF012H 4 P94 3 P93 2 P92 1 P91 0 P90 P9 0 P9n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 6) Remark In input mode: In output mode: When P9 is read, the pin levels at that time are read. Writing to P9 writes the values to that register. This does not affect the input pins. When P9 is read, the values of P9 are read. Writing to P9 writes the values to that register, and those values are immediately output. Port 9 includes the following alternate functions. Table 5-9. Port 9 Alternate-Function Pins Pin Name Port 9 P90 P91 P92 P93 P94 P95 P96 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ Alternate Function I/O I/O PULL No Note Remark - Note Software pull-up function User's Manual U14665EJ4V0UD 115 CHAPTER 5 PORT FUNCTION (1) Function of P9 pins Port 9 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 9 mode register (PM9). In output mode, the values set to each bit are output to port 9 (P9). When using this port in input mode, the pin statuses can be read by reading P9. Also, the values of P9 (output latch) can be read by reading P9 while in output mode. A software pull-up function is not implemented. When using P9 for control signals in expansion mode, set the pin functions via the memory expansion mode register (MM). When a reset is input, the settings are initialized to input mode. (2) Control register (a) Port 9 mode register (PM9) PM9 can be read/written in 8-bit or 1-bit units. After reset: 7FH 7 R/W 6 PM96 5 PM95 Address: FFFFF032H 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 PM9 0 PM9n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 6) 116 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (3) Block diagram (Port 9) Figure 5-10. Block Diagram of P90 to P96 RD Selector Internal bus WRPORT Output latch (P9n) P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ WRPM PM9 PM9n Remarks 1. PM9: Port 9 mode register RD: Port 9 read signal WR: Port 9 write signal 2. n = 0 to 6 User's Manual U14665EJ4V0UD 117 CHAPTER 5 PORT FUNCTION 5.2.9 Port 10 Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. A pull-up resistor can be connected in 1-bit units (software pull-up function). When using P100 to P107 as the KR0 to KR7 pins, noise is eliminated by an analog noise eliminator. After reset: 00H 7 R/W 6 P106 5 P105 Address: FFFFF014H 4 P104 3 P103 2 P102 1 P101 0 P100 P10 P107 P10n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 7) Remark In input mode: In output mode: When P10 is read, the pin levels at that time are read. Writing to P10 writes the values to that register. This does not affect the input pins. When P10 is read, the values of P10 are read. Writing to P10 writes the values to that register, and those values are immediately output. Port 10 includes the following alternate functions. Table 5-10. Port 10 Alternate-Function Pins Pin Name Port 10 P100 P101 P102 P103 P104 P105 P106 P107 Alternate Function KR0/TO7 KR1/TI70 KR2/TI00 KR3/TI01 KR4/TO0 KR5/TI10 KR6/TI11 KR7/TO1 I/O I/O PULL Yes Note Remark Analog noise elimination Note Software pull-up function 118 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (1) Function of P10 pins Port 10 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 10 mode register (PM10). In output mode, the values set to each bit are output to port 10 (P10). When using this port in input mode, the pin statuses can be read by reading P10. Also, the values of P10 (output latch) can be read by reading P10 while in output mode. A pull-up resistor can be connected in 1-bit units when specified via pull-up resistor option register 10 (PU10). When used as KR0 to KR7 pins, noise is eliminated by an analog noise eliminator. Clear P10 and the PM10 register to 0 when using alternate-function pins as outputs. The logical sum (ORed result) of the port output and the alternate-function pin is output from the pins. When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 10 mode register (PM10) PM10 can be read/written in 8-bit or 1-bit units. After reset: FFH 7 R/W 6 PM106 5 PM105 Address: FFFFF034H 4 PM104 3 PM103 2 PM102 1 PM101 0 PM100 PM10 PM107 PM10n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) (b) Pull-up resistor option register 10 (PU10) PU10 can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 PU106 5 PU105 Address: FFFFF094H 4 PU104 3 PU103 2 PU102 1 PU101 0 PU100 PU10 PU107 PU10n 0 1 Do not connect Connect Control of on-chip pull-up resistor connection (n = 0 to 7) User's Manual U14665EJ4V0UD 119 CHAPTER 5 PORT FUNCTION (3) Block diagram (Port 10) Figure 5-11. Block Diagram of P100 to P107 VDD WRPU PU10 PU10n P-ch RD Selector Internal bus WRPORT Output latch (P10n) WRPM PM10 PM10n P100/KR0/TO7 P101/KR1/TI70 P102/KR2/TI00 P103/KR3/TI01 P104/KR4/TO0 P105/KR5/TI10 P106//KR6/TI11 P107/KR7/TO1 Alternate function Remarks 1. PU10: Pull-up resistor option register 10 PM10: Port 10 mode register RD: WR: Port 10 read signal Port 10 write signal 2. n = 0 to 7 120 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.2.10 Port 11 Port 11 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. P11 can be read/written in 8-bit or 1-bit units. Turning on and off the wait function and switching between alternate pins and port pins can be performed via the port alternate-function control register (PAC) (CANTX2 and CANRX2 are available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y). After reset: 00H 7 R/W 6 P116 5 P115 Address: FFFFF016H 4 P114 3 P113 2 P112 1 P111 0 P110 P11 P117 P11n 0 1 Output 0 Output 1 Control of output data (in output mode) (n = 0 to 7) Remark In input mode: In output mode: When P11 is read, the pin levels at that time are read. Writing to P11 writes the values to that register. This does not affect the input pins. When P11 is read, the values of P11 are read. Writing to P11 writes the values to that register, and those values are immediately output. Port 11 includes the following alternate functions. Table 5-11. Port 11 Alternate-Function Pins Pin Name Port 11 P110 P111 P112 P113 P114 P115 P116 P117 WAIT - - - CANTX1 CANRX1 CANTX2 Note 2 Alternate Function I/O I/O PULL No Note 1 Remark - CANRX2 Note 2 Notes 1. Software pull-up function 2. Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y). User's Manual U14665EJ4V0UD 121 CHAPTER 5 PORT FUNCTION (1) Function of P11 pins Port 11 is an 8-bit port for which I/O settings can be controlled in 1-bit units. I/O settings are controlled via the port 11 mode register (PM11). In output mode, the values set to each bit are output to port 11 (P11). When using this port in input mode, the pin statuses can be read by reading P11. Also, the values of P11 (output latch) can be read by reading P11 while in output mode. Turning on and off the wait function and switching between alternate pins and port pins can be performed via the port alternate-function control register (PAC). When a reset is input, the settings are initialized to input mode. (2) Control registers (a) Port 11 mode register (PM11) PM11 can be read/written in 8-bit or 1-bit units. After reset: FFH 7 R/W 6 PM116 5 PM115 Address: FFFFF036H 4 PM114 3 PM113 2 PM112 1 PM111 0 PM110 PM11 PM117 PM11n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) (b) Port alternate-function control register (PAC) PAC can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 Note Address: FFFFF040H 5 Note 4 PAC114 3 0 2 0 1 0 0 WAC PAC PAC117 PAC116 PAC115 WAC 0 1 Wait function OFF Wait function ON Control of wait function PAC11n 0 1 Port function Alternate function Control of port alternate function (n = 4 to 7) Note Bits PAC117 and PAC116 are available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Set bits 7 and 6 to 0 when using the PD703075AY, 703078AY, and 703078Y. 122 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION (3) Block diagram (Port 11) Figure 5-12. Block Diagram of P110 and P114 to P117 RD Selector WRPORT Output latch (P11n) P110/WAIT P114/CANTX1 P115/CANRX1 P116/CANTX2 P117/CANRX2 Selector Internal bus WRPM PM11 PM11n PAC PAC11m, WAC Alternate function Remarks 1. PM11: Port 11 mode register RD: WR: PAC: Port 11 read signal Port 11 write signal Port alternate-function control register (PAC) 2. n = 0, 4 to 7 m = 4 to 7 User's Manual U14665EJ4V0UD 123 CHAPTER 5 PORT FUNCTION Figure 5-13. Block Diagram of P111 to P113 RD Selector Internal bus WRPORT Output latch (P11n) P111 to P113 WRPM PM11 PM11n Remarks 1. PM11: Port 11 mode register RD: WR: Port 11 read signal Port 11 write signal 2. n = 1 to 3 124 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.3 Setting When Port Pin Is Used for Alternate Function When a port pin is used for an alternate function, set the port n mode register (PM0 to PM6 and PM9 to PM11) and output latch as shown in Table 5-12 below. Table 5-12. Setting When Port Pin Is Used for Alternate Function (1/4) Alternate Function Function Name P00 NMI I/O Input PMnx Bit of PMn Register PM00 = 1 Pnx Bit of Pn Register Setting not needed for P00 P01 INTP0 Input PM01 = 1 Setting not needed for P01 P02 INTP1 Input PM02 = 1 Setting not needed for P02 P03 INTP2 Input PM03 = 1 Setting not needed for P03 P04 INTP3 Input PM04 = 1 Setting not needed for P04 P05 INTP4 ADTRG P06 INTP5 Input Input Input PM06 = 1 PM05 = 1 Setting not needed for P05 Setting not needed for P06 P07 INTP6 Input PM07 = 1 Setting not needed for P07 P10 SI0 Input PM10 = 1 Setting not needed for P10 SDA0 P11 P12 SO0 SCK0 I/O Output Input PM10 = 0 PM11 = 0 PM12 = 1 P10 = 0 P11 = 0 Setting not needed for P12 Output SCL0 P13 SI1 RXD0 P14 SO1 TXD0 P15 SCK1 I/O Input Input Output Output Input PM15 = 1 Setting not needed for P15 Output ASCK0 Input PM15 = 0 PM15 = 1 P15 = 0 Setting not needed for P15 PM14 = 0 PM13 = 1 Setting not needed for P13 P14 = 0 PM12 = 0 P12 = 0 PF12 = 1 PF10 = 1 Other Bits (Register) Pin Name User's Manual U14665EJ4V0UD 125 CHAPTER 5 PORT FUNCTION Table 5-12. Setting When Port Pin Is Used for Alternate Function (2/4) Alternate Function Function Name P20 SI3 RXD1 P21 SO2 TXD1 P22 SCK3 I/O Input Input Output Output Input PM22 = 1 Setting not needed for P22 Output ASCK1 Input PM22 = 0 PM22 = 1 P22 = 0 Setting not needed for P22 P23 SI4 Input PM23 = 1 Setting not needed for P23 P24 SO4 Output PM24 = 0 P24 = 0 PM21 = 0 PMnx Bit of PMn Register PM20 = 1 Pnx Bit of Pn Register Setting not needed for P20 P21 = 0 Other Bits (Register) Pin Name P25 SCK4 Input PM25 = 1 Setting not needed for P25 Output P30 TI2 Input PM25 = 0 PM30 = 1 P25 = 0 Setting not needed for P30 TO2 P31 TI3 Output Input PM30 = 0 PM31 = 1 P30 = 0 Setting not needed for P31 TO3 P32 TI4 Output Input PM31 = 0 PM32 = 1 P31 = 0 Setting not needed for P32 TO4 P33 TI5 Output Input PM32 = 0 PM33 = 1 P32 = 0 Setting not needed for P33 TO5 P34 TI71 Output Input PM33 = 0 PM34 = 1 P33 = 0 Setting not needed for P34 VM45 Output PM34 = 0 P34 = 0 Note Note Refer to 14.3 (2) VM45 control register (VM45C). 126 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION Table 5-12. Setting When Port Pin Is Used for Alternate Function (3/4) Alternate Function Function Name P40 to P47 AD0 to AD7 I/O I/O PMnx Bit of PMn Register Setting not needed for PM40 to PM47 P50 to P57 AD8 to AD15 I/O Setting not needed for PM50 to PM57 P60 to P65 A16 to A21 Output Setting not needed for PM60 to PM65 P70 to P77 ANI0 to ANI7 Input None Pnx Bit of Pn Register Setting not needed for P40 to P47 Setting not needed for P50 to P57 Setting not needed for P60 to P65 Setting not needed for P70 to P77 P80 to P83 ANI8 to ANI11 Input None Setting not needed for P80 to P83 P90 LBEN Output Setting not needed for PM90 P91 UBEN Output Setting not needed for PM91 P92 R/W Output Setting not needed for PM92 P93 DSTB Output Setting not needed for PM93 P94 ASTB Output Setting not needed for PM94 P95 HLDAK Output Setting not needed for PM95 P96 HLDRQ Input Setting not needed for PM96 Setting not needed for P95 Setting not needed for P96 Note Note P94 = 1 Note Setting not needed for P90 Setting not needed for P91 Setting not needed for P92 P93= 1 Note Note Note Note Note Note Note Other Bits (Register) Pin Name Note Refer to 3.4.6 (1) Memory expansion mode register (MM). User's Manual U14665EJ4V0UD 127 CHAPTER 5 PORT FUNCTION Table 5-12. Setting When Port Pin Is Used for Alternate Function (4/4) Alternate Function Function Name KR0 TO7 P101 KR1 TI70 P102 P103 KR2 TI00 KR3 TI01 P104 KR4 TO0 P105 KR5 TI10 P106 P107 KR6 TI11 KR7 TO1 P110 WAIT I/O Input Output Input Input Input Input Input Input Input Output Input Input Input Input Input Output Input PM107 = 1 PM107 = 0 PM110 = 1 PM106 = 1 PM104 = 1 PM104 = 0 PM105 = 1 PM103 = 1 PM102 = 1 PMnx Bit of PMn Register PM100 = 1 PM100 = 0 PM101 = 1 Pnx Bit of Pn Register Setting not needed for P100 P100 = 0 Setting not needed for P101 Setting not needed for P102 Setting not needed for P103 Setting not needed for P104 P104 = 0 Setting not needed for P105 Setting not needed for P106 Setting not needed for P107 P107 = 0 Setting not needed for P110 P114 P115 P116 P117 CANTX1 CANRX1 CANTX2 Note 1 Pin Name P100 Other Bits (Register) WAC = 1 (PAC) Output Input Output Input PM114 = 0 PM115 = 1 PM116 = 0 PM117 = 1 Setting not needed for P114 Setting not needed for P115 Setting not needed for P116 Setting not needed for P117 PAC114 = 1 (PAC) PAC115 = 1 (PAC) PAC116 = 1 (PAC) PAC117 = 1 (PAC) Note 1 Notes 1, 2 CANRX2 Notes 1, 2 Notes 1. 2. When the CAN alternate function is selected by the PAC register, initialize the CAN. For details, refer to 18.16 <9>. Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Caution When changing the output level of port 0 by setting the port function output mode of port 0, the interrupt request flag will be set because port 0 also has an alternate function as external interrupt request input. Therefore, be sure to set the corresponding interrupt mask flag to 1 before using a port 0 pin as an output pin. Remark PMnx bit of PMn register and Pnx bit of Pn register n: 0 (x = 0 to 7) n: 5 (x = 0 to 7) n: 10 (x = 0 to 7) n: 1 (x = 0 to 5) n: 6 (x = 0 to 5) n: 11 (x = 0 to 7) n: 2 (x = 0 to 7) n: 7 (x = 0 to 7) n: 3 (x = 0 to 4) n: 8 (x = 0 to 3) n: 4 (x = 0 to 7) n: 9 (x = 0 to 6) 128 User's Manual U14665EJ4V0UD CHAPTER 5 PORT FUNCTION 5.4 Operation of Port Function The operation of a port differs depending on whether the port is in the input or output mode, as described below. 5.4.1 Writing data to I/O port (1) In output mode A value can be written to the output latch by using a transfer instruction. The contents of the output latch are output from the pin. Once data has been written to the output latch, it is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. Because the output buffer is off, however, the status of the pin does not change. Once data has been written to the output latch, it is retained until new data is written to the output latch. Caution A bit manipulation instruction (CLR1, SET1, NOT1) manipulates 1 bit but accesses a port in 8-bit units. If this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 5.4.2 Reading data from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch do not change. (2) In input mode The status of the pin can be read by using a transfer instruction. The contents of the output latch do not change. User's Manual U14665EJ4V0UD 129 CHAPTER 6 BUS CONTROL FUNCTION The V850/SF1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 6.1 Features * * * * Address bus 16-bit data bus Able to be connected to external devices via pins with alternate-functions as ports Wait function * Programmable wait function, capable of inserting up to 3 wait states per 2 blocks * * * * External wait control through WAIT input pin Idle state insertion function Bus mastership arbitration function Bus hold function 6.2 Bus Control Pins and Control Register 6.2.1 Bus control pins The following pins are used for interfacing with external devices. Table 6-1. Bus Control Pins External Bus Interface Function Address/data bus (AD0 to AD7) Address/data bus (AD8 to AD15) Address bus (A16 to A21) Read/write control (LBEN, UBEN, R/W, DSTB) Address strobe (ASTB) Bus hold control (HLDRQ, HLDAK) External wait control (WAIT) Corresponding Port (Pins) Port 4 (P40 to P47) Port 5 (P50 to P57) Port 6 (P60 to P65) Port 9 (P90 to P93) Port 9 (P94) Port 9 (P95, P96) Port 11 (P110) The bus interface function of each pin is enabled by setting the memory expansion mode register (MM). For details of external bus interface operating mode specification, refer to 3.4.6 (1) Memory expansion mode register (MM). 130 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION 6.3 Bus Access 6.3.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Table 6-2. Number of Access Clocks Peripheral I/O (Bus Width) Bus Cycle Type Internal ROM (32 Bits) Instruction fetch Operand data access 1 3 Internal RAM (32 Bits) 3 1 Peripheral I/O (16 Bits) Disabled 3 External Memory (16 Bits) 3+n 3+n Remarks 1. Unit: Clock/access 2. n: Number of wait insertions User's Manual U14665EJ4V0UD 131 CHAPTER 6 BUS CONTROL FUNCTION 6.3.2 Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types: access to even addresses and access to odd addresses. Figure 6-1. Byte Access (8 Bits) (a) Access to even address 15 (b) Access to odd address 15 7 8 7 7 8 7 0 Byte data 0 External data bus 0 Byte data 0 External data bus (2) Halfword access (16 bits) In halfword access to external memory, data is handled as is because the data bus is fixed to 16 bits. Figure 6-2. Halfword Access (16 Bits) 15 15 0 Halfword data 0 External data bus (3) Word access (32 bits) In word access to external memory, the lower halfword is accessed first and then the higher halfword is accessed. Figure 6-3. Word Access (32 Bits) First 31 31 Second 16 15 15 16 15 15 0 Word data 0 External data bus 0 Word data 0 External data bus 132 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION 6.4 Memory Block Function The 16 MB memory space is divided into memory blocks of 1 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. Figure 6-4. Memory Block FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH Block 10 A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 400000H 3FFFFFH Block 3 300000H 2FFFFFH Block 2 200000H 1FFFFFH Block 1 100000H 0FFFFFH Block 0 000000H Internal ROM area Block 5 Block 4 Block 9 Block 8 External memory area Block 7 Block 6 Block 15 Block 14 Internal RAM area Block 13 Block 12 Block 11 On-chip peripheral I/O area User's Manual U14665EJ4V0UD 133 CHAPTER 6 BUS CONTROL FUNCTION 6.5 Wait Function 6.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle that starts every two memory blocks. The number of wait states can be programmed by using the data wait control register (DWC). Immediately after the system has been reset, three data wait states are automatically programmed for insertion in all memory blocks. (1) Data wait control register (DWC) This register can be read/written in 16-bit units. After reset: FFFFH 15 DWC 14 R/W 13 12 11 Address: FFFFF060H 10 9 8 7 6 5 4 3 2 1 0 DW71 DW70 DW61 DW60 DW51 DW50 DW41 DW40 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00 DWn1 DWn0 0 0 1 1 0 1 0 1 Number of wait states to be inserted 0 1 2 3 n 0 1 2 3 4 5 6 7 Blocks 0/1 Blocks 2/3 Blocks 4/5 Blocks 6/7 Blocks 8/9 Blocks 10/11 Blocks 12/13 Blocks 14/15 Blocks into which wait states are inserted Block 0 is reserved for the internal ROM area. It is not subject to programmable wait control, regardless of the setting of DWC, and is always accessed without wait states. The internal RAM area of block 15 is not subject to programmable wait control and is always accessed without wait states. The on-chip peripheral I/O area of this block is not subject to programmable wait control, either. The wait control is dependent upon the execution of each peripheral function. 134 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION 6.5.2 External wait function When an extremely slow memory, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is for data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait. The external WAIT signal can be input asynchronously to CLKOUT and is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle. If the setup/hold time at the sampling timing is not satisfied, the wait state may or may not be inserted in the next state. Caution The P110 pin and WAIT pin are alternate-function pins. Set bit 0 (WAC) of the port alternate function control register (PAC) to 1 when these pins are used for the wait function. 6.5.3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by the set value of a programmable wait and the wait cycle controlled by the WAIT pin. Figure 6-5. Wait Control Programmable wait Wait control Wait by WAIT pin For example, if the number of programmable waits and the timing of the WAIT pin input signal are as illustrated below, three wait states will be inserted in the bus cycle. Figure 6-6. Example of Inserting Wait States T1 CLKOUT WAIT pin Wait by WAIT pin Programmable wait Wait control T2 TW TW TW T3 Remark : Valid sampling timing User's Manual U14665EJ4V0UD 135 CHAPTER 6 BUS CONTROL FUNCTION 6.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle following continuous bus cycles starts after one idle state. Specifying insertion of the idle state is programmable by using the bus cycle control register (BCC). Immediately after the system has been reset, idle state insertion is automatically programmed for all memory blocks. (1) Bus cycle control register (BCC) This register can be read/written in 16-bit units. After reset: AAAAH 15 BCC BC71 14 0 R/W 13 BC61 12 0 11 BC51 Address: FFFFF062H 10 0 9 BC41 8 0 7 BC31 6 0 5 BC21 4 0 3 BC11 2 0 1 BC01 0 0 BCn1 0 1 Not inserted Inserted Idle state insert specification n 0 1 2 3 4 5 6 7 Blocks 0/1 Blocks 2/3 Blocks 4/5 Blocks 6/7 Blocks 8/9 Blocks 10/11 Blocks 12/13 Blocks 14/15 Blocks into which idle state is inserted Block 0 is reserved for the internal ROM area and therefore no idle state can be specified. The internal RAM area and on-chip peripheral I/O area of block 15 are not subject to insertion of an idle state. Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to 0. If these bits are set to 1, the operation is not guaranteed. 136 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION 6.7 Bus Hold Function 6.7.1 Outline of function When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of P95 and P96 become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state, and the bus is released (bus hold status). When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins are driven again. During the bus hold period, the internal operation continues until the next external memory access. The bus hold status can be recognized by the HLDAK pin becoming active (low). This feature can be used to design a system where two or more bus masters exist, such as when a multi-processor configuration is used and when a DMA controller is connected. Bus hold requests are not acknowledged between the first and the second word access, nor between a read access and a write access in the read modify write access of a bit manipulation instruction. User's Manual U14665EJ4V0UD 137 CHAPTER 6 BUS CONTROL FUNCTION 6.7.2 Bus hold procedure The procedure of the bus hold function is illustrated below. Figure 6-7. Bus Hold Procedure <1>HLDRQ = 0 acknowledged <2>All bus cycle start requests pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 Normal status Bus hold status <6>HLDRQ = 1 acknowledged <7>HLDAK = 1 <8>Clears bus cycle start requests pending <9>Start of bus cycle Normal status HLDRQ HLDAK <1> <2> <3><4><5> <6> <7><8><9> 6.7.3 Operation in power save mode In the IDLE or STOP mode, the system clock is stopped. Consequently, the bus hold status is not set even if the HLDRQ pin becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold status is set. When the HLDRQ pin becomes inactive, the HLDAK pin becomes inactive. As a result, the bus hold status is cleared, and the HALT mode is set again. 138 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION 6.8 Bus Timing The V850/SF1 can execute read/write control for an external device using the following mode. * Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals Figure 6-8. Memory Read (1/4) (a) 0 waits T1 CLKOUT (output) T2 T3 A16 to A21 (output) Address AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. The broken lines indicate the high-impedance state. User's Manual U14665EJ4V0UD 139 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (2/4) (b) 1 wait T1 CLKOUT (output) T2 TW T3 A16 to A21 (output) Address AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number of programmable waits is set to 1. 2. The broken lines indicate the high-impedance state. 140 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (3/4) (c) 0 waits, idle state T1 CLKOUT (output) T2 T3 TI A16 to A21 (output) Address AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. The broken lines indicate the high-impedance state. User's Manual U14665EJ4V0UD 141 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-8. Memory Read (4/4) (d) 1 wait, idle state T1 CLKOUT (output) T2 TW T3 TI A16 to A21 (output) Address AD0 to AD15 (I/O) Address Data ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number of programmable waits is set to 1. 2. The broken lines indicate the high-impedance state. 142 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION Figure 6-9. Memory Write (1/2) (a) 0 waits T1 CLKOUT (output) T2 T3 A16 to A21 (output) Address AD0 to AD15 (I/O) Address DataNote ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Note AD0 to AD7 output invalid data when odd-address byte data is accessed. AD8 to AD15 output invalid data when even-address byte data is accessed. Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. The broken lines indicate the high-impedance state. User's Manual U14665EJ4V0UD 143 CHAPTER 6 BUS CONTROL FUNCTION Figure 6-9. Memory Write (2/2) (b) 1 wait T1 CLKOUT (output) T2 TW T3 A16 to A21 (output) Address AD0 to AD15 (I/O) Address DataNote ASTB (output) R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Note AD0 to AD7 output invalid data when odd-address byte data is accessed. AD8 to AD15 output invalid data when even-address byte data is accessed. Remarks 1. indicates the sampling timing when the number of programmable waits is set to 1. 2. The broken lines indicate the high-impedance state. 144 User's Manual U14665EJ4V0UD CHAPTER 6 BUS CONTROL FUNCTION Figure 6-10. Bus Hold Timing T2 T3 TH TH TH TH TI T1 CLKOUT (output) HLDRQ (input) Note 1 HLDAK (output) A16 to A21 (output) Address Address AD0 to AD15 (I/O) Address Data Undefined Address ASTB (output) Note 2 R/W (output) DSTB (output) UBEN, LBEN (output) WAIT (input) Notes 1. If the HLDRQ signal is inactive (high level) at this sampling timing, the bus hold state is not entered. 2. If transferred to the bus hold states after a write cycle, a high level may be output momentarily from the R/W pin immediately before the HLDAK signal changes from high level to low level. Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2. The broken lines indicate the high-impedance state. User's Manual U14665EJ4V0UD 145 CHAPTER 6 BUS CONTROL FUNCTION 6.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order. The instruction fetch cycle may be inserted in between a read access and a write access in a read-modify-write access. No instruction fetch cycle and bus hold are inserted between the lower halfword access and the higher halfword access in word access operations. Table 6-3. Bus Priority External Bus Cycle Bus hold Operand data access Instruction fetch (branch) Instruction fetch (continuous) Priority 1 2 3 4 6.10 Memory Boundary Operation Condition 6.10.1 Program space (1) Do not execute a branch to the on-chip peripheral I/O area or a continuous fetch from the internal RAM area to the peripheral I/O area. If a branch or instruction fetch is executed, the NOP instruction code is continuously fetched and fetching from external memory is not performed. (2) A prefetch operation extending over the on-chip peripheral I/O area (invalid fetch) does not take place if a branch instruction exists at the upper-limit address of the internal RAM area. 6.10.2 Data space Only the address aligned at the halfword boundary (when the least significant bit of the address is "0")/word boundary (when the lowest 2 bits of the address are "0") is accessed by halfword (16 bits)/word (32 bits) access, respectively. Therefore, access that extends over the memory or memory block boundary does not take place. For details, refer to V850 Series Architecture User's Manual. 146 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.1 Outline The V850/SF1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realizes a highpowered interrupt function that can service interrupt requests from a total of 41 sources (PD703075AY, 703078AY, 703078Y)/44 sources (PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y). An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependent on program execution. The V850/SF1 can service interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started (exception trap) by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal opcode). 7.1.1 Features * Interrupts * * Non-maskable interrupts: 2 sources Maskable interrupts (the number of maskable interrupt sources differs depending on the product): PD703075AY, 703078AY, 703078Y: 41 sources PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y: 44 sources * * * * * 8 levels of programmable priorities Mask specification for interrupt requests according to priority Masks can be specified for each maskable interrupt request. Noise elimination, edge detection, and the valid edge of an external interrupt request signal can be specified. Exceptions * * Software exceptions: 32 sources Exception trap: 1 source (illegal opcode exception) The interrupt/exception sources are listed in Table 7-1. User's Manual U14665EJ4V0UD 147 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (1/2) Interrupt Restored Control PC Register Undefined nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC - - - - - - WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIC4 ADIC DMA0 DMA1 DMA2 TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC3 WTNIC WTNIIC CSIC0 SERIC0 CSIC1 STIC0 Type Reset Nonmaskable Software exception Classification Interrupt Interrupt Interrupt Exception Exception Default Priority - - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name RESET NMI INTWDT TRAP0n TRAP1n ILGOP INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI4 INTAD INTDMA0 INTDMA1 INTDMA2 INTTM00 INTTM01 INTTM10 INTTM11 INTTM2 INTTM3 INTTM4 INTTM5 INTWTN INTWTNI INTIIC0/ INTCSI0 INTSER0 INTSR0/ INTCSI1 INTST0 Note Trigger Reset input NMI pin input WDTOVF non-maskable TRAP instruction TRAP instruction Illegal opcode WDTOVF maskable INTP0 pin INTP1 pin INTP2 pin INTP3 pin INTP4 pin INTP5 pin INTP6 pin CSI4 transmit end A/D conversion end DMA0 transfer end DMA1 transfer end DMA2 transfer end TM0 and CR00 match/ TI01 pin valid edge TM1 and CR01 match/ TI00 pin valid edge TM1 and CR10 match/ TI11 pin valid edge TM1 and CR11 match/ TI10 pin valid edge Interrupt Exception Source Code - - WDT - - - WDT Pin Pin Pin Pin Pin Pin Pin SIO4 A/D DMA0 DMA1 DMA2 TM0 TM0 TM1 TM1 0000H 0010H 0020H 004nH 005nH Note Handler Address 00000000H 00000010H 00000020H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H Note Note Exception Exception trap Maskable Interrupt 0060H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01C0H 01D0H 01E0H 01F0H TM2 compare match/OVF TM2 TM3 compare match/OVF TM3 TM4 compare match/OVF TM4 TM5 compare match/OVF TM5 Watch timer OVF Watch timer prescaler I C interrupt/ CSI0 transmit end UART0 serial error UART0 receive end/ CSI1 transmit end UART0 transmit end 2 WT WTN I C/ CSI0 2 UART0 0200H UART0/ 0210H CSI1 UART0 0220H Note n: 0 to FH 148 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (2/2) Interrupt Control Register KRIC CANIC1 CANIC2 CANIC3 CANIC7 Type Classification Interrupt Default Priority 27 28 29 30 31 Name Trigger Interrupt Exception Source KR FCAN1 FCAN1 FCAN1 FCAN1/ 2 TM6 0280H Code 0230H 0240H 0250H 0260H 0270H Handler Address 00000230H 00000240H 00000250H 00000260H 00000270H Restored PC nextPC nextPC nextPC nextPC nextPC Maskable INTKR INTCE1 INTCR1 INTCT1 INTCME Key return interrupt FCAN1 serial error FCAN1 reception FCAN1 transmission FCAN memory access error 32 INTTM6 TM6 compare match/ OVF 00000280H nextPC TMIC6 33 INTTM70 TM7 and CR70 match/ TI71 pin valid edge TM7 0290H 00000290H nextPC TMIC70 34 INTTM71 TM71 and CR71 match/ TI70 pin valid edge TM7 02A0H 000002A0H nextPC TMIC71 35 36 INTSER1 INTSR1/ INTCSI3 UART1 serial error UART1 receive end/ CSI3 transmit end UART1 transmit end DMA3 transfer end DMA4 transfer end DMA5 transfer end FCAN2 serial error FCAN2 reception FCAN2 transmission UART1 UART1/ CSI3 UART1 DMA3 DMA4 DMA5 FCAN2 FCAN2 FCAN2 02B0H 02C0H 000002B0H 000002C0H nextPC nextPC SERIC1 CSIC3 37 38 39 40 41 42 43 INTST1 INTDMA3 INTDMA4 INTDMA5 INTCE2 Note 02D0H 02E0H 02F0H 0300H 0310H 0320H 0330H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H nextPC nextPC nextPC nextPC nextPC nextPC nextPC STIC1 DMAIC3 DMAIC4 DMAIC5 CANIC4 CANIC5 CANIC6 INTCR2 INTCT2 Note Note Note Available only in the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Remarks 1. Default Priority: Restored PC: The priority when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The value of the PC saved to EIPC or FEPC when interrupt/exception processing is started. However, the value of the PC saved when an interrupt is acknowledged during the DIVH (division) instruction execution is the value of the PC of the current instruction (DIVH). 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). 3. The restored PC of an interrupt/exception other than RESET is the value of (the PC when an event occurred) + 1. 4. Non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM) are set by the WDTM4 bit of the watchdog timer mode register (WDTM). User's Manual U14665EJ4V0UD 149 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are available in the V850/SF1. * * NMI pin input (NMI) Non-maskable watchdog timer interrupt request (INTWDT) When the valid edge specified by rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) is detected at the NMI pin, an interrupt occurs. INTWDT functions as a non-maskable interrupt (INTWDT) only when the WDTM4 bit of the watchdog timer mode register (WDTM) is set to 1. While the service routine of a non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgement of another non-maskable interrupt request is held pending. The pending NMI is acknowledged when PSW.NP is cleared to 0 after the original service routine of the non-maskable interrupt under execution has been terminated (by the RETI instruction). Note that if two or more NMI requests are input during the execution of the service routine for an NMI, only one NMI will be acknowledged after PSW.NP is cleared to 0. Caution Do not clear PSW.NP to 0 by the LDSR instruction during non-maskable interrupt servicing. If PSW.NP is cleared to 0, the interrupts afterwards cannot be acknowledged correctly. 150 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. (4) Sets the NP and ID bits of the PSW and clears the EP bit. (5) Loads the handler address (00000010H, 00000020H) of the non-maskable interrupt routine to the PC, and transfers control. Figure 7-1. Non-Maskable Interrupt Servicing NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW. NP 0 1 FEPC FEPSW ECR. FECC PSW. NP PSW. EP PSW. ID PC restored PC PSW exception code 1 0 1 Handler address Interrupt request pending Handler address: 00000010H (NMI) 00000020H (INTWDT) Interrupt servicing User's Manual U14665EJ4V0UD 151 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Requests (a) If a new NMI request is generated while an NMI service routine is being executed Main routine (PSW. NP = 1) NMI request NMI request NMI request held pending regardless of NP bit of PSW Pending NMI request serviced (b) If a new NMI request is generated twice while an NMI service routine is being executed Main routine NMI request NMI request NMI request Held pending because NMI service program is being processed Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two or more NMI requests are generated 152 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. (2) Transfers control back to the address of the restored PC and PSW. How the RETI instruction is processed is shown below. Figure 7-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during restoration by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. User's Manual U14665EJ4V0UD 153 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to prohibit multiple interrupts from being acknowledged. Figure 7-4. NP Flag (NP) After reset: 00000020H 31 PSW 0 8 7 6 5 4 3 2 1 S 0 Z NP EP ID SAT CY OV NP 0 1 No NMI interrupt servicing NMI servicing state NMI interrupt currently being serviced 7.2.4 Noise elimination of NMI pin NMI pin noise is eliminated by the noise eliminator using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge, unless it maintains its input level for a certain period. The edge is detected after a certain period has elapsed. The NMI pin is used for releasing the software stop mode. In the software stop mode, noise elimination using the system clock does not occur because the internal system clock is stopped. 154 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, neither rising nor falling edge detected. Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge of a non-maskable interrupt (NMI). These two registers can be read/written in 1-bit or 8-bit units. After reset, the valid edge of the NMI pin is set to the "neither rising nor falling edge detected" state. Therefore, the NMI pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the EGP0 and EGN0 registers. When using P00 as an output port, set the NMI valid edge to "neither rising nor falling edge detected". (1) Rising edge specification register 0 (EGP0) After reset: 00H 7 EGP0 EGP07 R/W 6 EGP06 5 EGP05 Address: FFFFF0C0H 4 EGP04 3 EGP03 2 EGP02 1 EGP01 0 EGP00 EGP0n 0 1 Rising edge valid control No interrupt request signal occurs at the rising edge Interrupt request signal occurs at the rising edge n = 0: NMI pin control n = 1 to 7: INTP0 to INTP6 pins control (2) Falling edge specification register 0 (EGN0) After reset: 00H 7 EGN0 EGN07 R/W 6 EGN06 5 EGN05 Address: FFFFF0C2H 4 EGN04 3 EGN03 2 EGN02 1 EGN01 0 EGN00 EGN0n 0 1 Falling edge valid control No interrupt request signal occurs at the falling edge Interrupt request signal occurs at the falling edge n = 0: NMI pin control n = 1 to 7: INTP0 to INTP6 pins control User's Manual U14665EJ4V0UD 155 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850/SF1 has 41 (PD703075AY, 703078AY, 703078Y)/44 (PD703076AY, 703079AY, 703079Y, 70F3079AY, 70F3079Y) maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers, allowing programmable priority control. When an interrupt request has been acknowledged, the acknowledgement of other maskable interrupts is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which enables interrupts having a higher priority to immediately interrupt the service routine in currently progress. Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction. When the WDTM4 bit of the watchdog timer mode register (WDTM) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (INTWDTM). 7.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower halfword of ECR (EICC). (4) Sets the ID bit of the PSW and clears the EP bit. (5) Loads the corresponding handler address to the PC, and transfers control. The INT input masked by INTC and the INT input that occurs while another interrupt is being serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally. When the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT is input to start new maskable interrupt servicing. How maskable interrupts are serviced is shown below. 156 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-5. Maskable Interrupt Servicing INT input INTC acknowledged Mask? No PSW. ID = 0 Yes Priority higher than that of interrupt currently being serviced? Yes No Interrupt enable mode? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request CPU processing 1 PSW. NP 0 1 PSW. ID 0 EIPC EIPSW ECR. EICC PSW. EP PSW. ID PC restored PC PSW exception code 0 1 handler address Interrupt request pending Interrupt request pending Interrupt servicing User's Manual U14665EJ4V0UD 157 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore To restore execution from maskable interrupt servicing, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of PSW is 0. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 7-6. RETI Instruction Processing RETI instruction 1 PSW. EP 0 1 PSW. NP 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Restores original processing Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the maskable interrupt service, in order to restore the PC and PSW correctly during restoration by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. 158 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850/SF1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxPRn). When two or more interrupts having the same priority level specified by xxPRn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, refer to Table 7-1. Programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request is acknowledged, the ID flag of the PSW is automatically set (1). Therefore, when multiple interrupts are to be used, clear (0) the ID flag beforehand (for example, by placing the EI instruction into the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) User's Manual U14665EJ4V0UD 159 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Multiple Interrupt (1/2) Main routine Servicing of a EI Interrupt request a (level 3) Interrupt request b (level 2) EI Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Servicing of d Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Servicing of f Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Servicing of h Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts. Remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests. 160 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Multiple Interrupt (2/2) Main routine Servicing of i EI Interrupt request i (level 2) EI Interrupt request j (level 3) Interrupt request k (level 1) Servicing of k Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request l (level 2) Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q EI Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request t (level 2) Interrupt request u (level 2) Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Interrupt request s (level 1) Note 1 Note 2 Servicing of u Servicing of t Notes 1. 2. Lower default priority Higher default priority User's Manual U14665EJ4V0UD 161 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-8. Example of Servicing Interrupt Requests Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Note 1 Interrupt request c (level 1) Note 2 Servicing of interrupt request b * Interrupt request b and c are acknowledged first according to their priorities. * Because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. Servicing of interrupt request c Servicing of interrupt request a Notes 1. 2. Higher default priority Lower default priority Remarks 1. a to c in the above figure are the names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests. 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Caution If the following three conditions conflict, interrupt servicing is executed twice. However, when DMA is not used, interrupt servicing is not executed twice. * * * Execution of a bit manipulation instruction corresponding to the interrupt request flag (xxIFn) An interrupt of the same interrupt control register (xxICn) as the interrupt request flag (xxIFn) is generated via hardware DMA is started during execution of a bit manipulation instruction corresponding to the interrupt request flag (xxIFn) Two workarounds using software are shown below. * Insert a DI instruction before the software-based bit manipulation instruction and an EI instruction after it, so that jumping to an interrupt immediately after the bit manipulation instruction execution does not occur. * When an interrupt request is acknowledged, since the hardware becomes interrupt disabled (DI state), clear the interrupt request flag (xxIFn) before executing the EI instruction in each interrupt servicing routine. 162 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: 47H 7 xxICn R/W Address: FFFFF100H to FFFFF156H 6 xxMKn 5 0 4 0 3 0 2 xxPRn2 1 xxPRn1 0 xxPRn0 xxIFn xxIFn 0 1 Interrupt request flag Interrupt request not generated Interrupt request generated Note xxMKn 0 1 Interrupt servicing enabled Interrupt mask flag Interrupt servicing disabled (pending) xxPRn2 0 0 0 0 1 1 1 1 xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 Interrupt priority specification bit Specifies level 0 (highest) Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 (lowest) Note Automatically reset by hardware when interrupt request is acknowledged. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) User's Manual U14665EJ4V0UD 163 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The addresses and bits of each interrupt control register are as follows. Table 7-2. Interrupt Control Registers (xxICn) Bit 7 WDTIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 CSIF4 ADIF DMAIF0 DMAIF1 DMAIF2 TMIF00 TMIF01 TMIF10 TMIF11 TMIF2 TMIF3 TMIF4 TMIF5 WTNIF WTNIIF CSIF0 SERIF0 CSIF1 STIF0 KRIF CANIF1 CANIF2 CANIF3 CANIF7 TMIF6 TMIF70 TMIF71 SERIF1 CSIF3 STIF1 DMAIF3 DMAIF4 DMAIF5 CANIF4 CANIF5 CANIF6 6 WDTMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 CSMK4 ADMK DMAMK0 DMAMK1 DMAMK2 TMMK00 TMMK01 TMMK10 TMMK11 TMMK2 TMMK3 TMMK4 TMMK5 WTNMK WTNIMK CSMK0 SERMK0 CSMK1 STMK0 KRMK CANMK1 CANMK2 CANMK3 CANMK7 TMMK6 TMMK70 TMMK71 SERMK1 CSMK3 STMK1 DMAMK3 DMAMK4 DMAMK5 CANMK4 CANMK5 CANMK6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 WDTPR2 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 CSPR42 ADPR2 DMAPR02 DMAPR12 DMAPR22 TMPR002 TMPR012 TMPR102 TMPR112 TMPR22 TMPR32 TMPR42 TMPR52 WTNPR2 WTNIPR2 CSPR02 SERPR02 CSPR12 STPR02 KRPR2 CANPR12 CANPR22 CANPR32 CANPR72 TMPR62 TMPR702 TMPR712 SERPR12 CSPR32 STPR12 DMAPR32 DMAPR42 DMAPR52 CANPR42 CANPR52 CANPR62 1 WDTPR1 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 CSPR41 ADPR1 DMAPR01 DMAPR11 DMAPR21 TMPR001 TMPR011 TMPR101 TMPR111 TMPR21 TMPR31 TMPR41 TMPR51 WTNPR1 WTNIPR1 CSPR01 SERPR01 CSPR11 STPR01 KRPR1 CANPR11 CANPR21 CANPR31 CANPR71 TMPR61 TMPR701 TMPR711 SERPR11 CSPR31 STPR11 DMAPR31 DMAPR41 DMAPR51 CANPR41 CANPR51 CANPR61 0 WDTPR0 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60 CSPR40 ADPR0 DMAPR00 DMAPR10 DMAPR20 TMPR000 TMPR010 TMPR100 TMPR110 TMPR20 TMPR30 TMPR40 TMPR50 WTNPR0 WTNIPR0 CSPR00 SERPR00 CSPR10 STPR00 KRPR0 CANPR10 CANPR20 CANPR30 CANPR70 TMPR60 TMPR700 TMPR710 SERPR10 CSPR30 STPR10 DMAPR30 DMAPR40 DMAPR50 CANPR40 CANPR50 CANPR60 Address FFFFF100H FFFFF102H FFFFF104H FFFFF106H FFFFF108H FFFFF10AH FFFFF10CH FFFFF10EH FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H Register WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIC4 ADIC DMAIC0 DMAIC1 DMAIC2 TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 TMIC5 WTNIC WTNIIC CSIC0 SERIC0 CSIC1 STIC0 KRIC CANIC1 CANIC2 CANIC3 CANIC7 TMIC6 TMIC70 TMIC71 SERIC1 CSIC3 STIC1 DMAIC3 DMAIC4 DMAIC5 CANIC4 CANIC5 CANIC6 Note Note Note Note Available only for the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. 164 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset (0) by hardware. However, it is not reset (0) when execution is returned from non-maskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI status). After reset: 00H 7 ISPR ISPR7 6 ISPR6 R 5 ISPR5 Address: FFFFF166H 4 ISPR4 3 ISPR3 2 ISPR2 1 ISPR1 0 ISPR0 ISPRn 0 1 Indicates priority of interrupt currently acknowledged Interrupt request with priority n not acknowledged Interrupt request with priority n acknowledged Remark n: 0 to 7 (priority level) User's Manual U14665EJ4V0UD 165 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 ID flag The ID flag controls the operating status of maskable interrupt requests and stores the enable/disable control information of interrupt requests. It is allocated in the PSW. Figure 7-9. ID Flag After reset: 00000020H 31 PSW 0 8 7 6 5 4 3 2 1 S 0 Z NP EP ID SAT CY OV ID 0 1 Maskable interrupt servicing specification Maskable interrupt acknowledgement enabled Maskable interrupt acknowledgement disabled (pending) Note Note Interrupt disable flag (ID) function It is set (1) by the DI instruction and reset (0) by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupts and exceptions are acknowledged regardless of this flag. When a maskable interrupt is acknowledged, the ID flag is automatically set (1) by hardware. An interrupt request generated during the acknowledgement disabled period (ID = 1) can be acknowledged when the xxIFn bit of xxICn is set (1), and the ID flag is reset (0). Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 166 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Watchdog timer mode register (WDTM) This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 10 WATCHDOG TIMER FUNCTION). After reset: 00H 7 WDTM RUN 6 0 R/W 5 0 Address: FFFFF384H 4 WDTM4 3 0 2 0 1 0 0 0 RUN 0 1 Count operation stopped Watchdog timer operation control Count started after clearing WDTM4 0 1 Timer mode selection/interrupt control by WDT Interval timer mode WDT mode Caution If the RUN or WDTM4 bit is set to 1, that bit can only be cleared by reset input. 7.3.8 Noise elimination (1) Noise elimination of INTP0 to INTP3 pins The INTP0 to INTP3 pins incorporate a noise eliminator that functions via analog delay. Therefore, a signal input to each pin is not detected as an edge, unless it maintains its input level for a certain period. An edge is detected after a certain period has elapsed. (2) Noise elimination of INTP4 and INTP5 pins The INTP4 and INTP5 pins incorporate a digital noise eliminator. If an input level of the INTP pin is detected by the sampling clock (fxx) and the same level is not detected three successive times, the input pulse is eliminated as a noise. Note the following: * * If the input pulse width is 2 to 3 clocks, whether it is detected as a valid edge or eliminated as a noise is undetermined. To securely detect the valid edge, the same level input of 3 clocks or more is required. When noise is generated in synchronization with the sampling clock, this may not be recognized as noise. In this case, eliminate the noise by adding a filter to the input pin. User's Manual U14665EJ4V0UD 167 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Noise elimination of INTP6 pin The INTP6 pin incorporates a digital noise eliminator. The sampling clock for digital sampling can be selected from among fXX, fXX/64, fXX/128, fXX/256, fXX/512, fXX/1024, and fXT. Sampling is performed 3 times. The noise elimination control register (NCC) selects the clock to be used. Remote control signals can be received effectively with this function. fXT can be used for the noise elimination clock. In this case, the INTP6 external interrupt function is enabled in the IDLE/STOP mode. This register can be read/written in 8-bit or 1-bit units. Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the noise eliminator. For that reason, if an INTP6 valid edge was input within these 3 clocks, an interrupt request may occur. Therefore, observe the following points when using the interrupt and DMA functions. * * When using the interrupt function, after 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (bit 7 of PIC6) has been cleared. When using the DMA function, after 3 sampling clocks have elapsed, enable DMA by setting bit 0 of DCHCn. (a) Noise elimination control register (NCC) After reset: 00H 7 NCC 0 R/W Address: FFFFF3D4H 6 0 5 0 4 0 3 0 2 NCS2 1 NCS1 0 NCS0 Reliably eliminated noise width NCS2 0 0 0 0 1 1 1 1 NCS1 0 0 1 1 0 0 1 1 NCS0 0 1 0 1 0 1 0 1 fXX fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 Setting prohibited fXT 61 s Sampling clock fXX = 16 MHz 125.0 ns 8.0 s 16.0 s 32.0 s 64.0 s 128.0 s fXX = 8 MHz 250.0 ns 16.0 s 32.0 s 64.0 s 128.0 s 256.0 s Note Note Since sampling is preformed three times, the reliably eliminated noise width is 2 x noise elimination clock. 168 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.9 Edge detection function The valid edges of the INTP0 to INTP6 pins can be selected for each pin from the following four types. * Rising edge * Falling edge * Both rising and falling edges * Neither rising nor falling edge detected The validity of the rising edge is controlled by rising edge specification register 0 (EGP0), and the validity of the falling edge is controlled by falling edge specification register 0 (EGN0). Refer to 7.2.5 Edge detection function of NMI pin for details of EGP0 and EGN0. After reset, the valid edge of the NMI pin is set to the "neither rising nor falling edge detected" state. Therefore, the NMI pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified by using the EGP0 and EGN0 registers. When using P01 to P07 as output ports, set the valid edges of INTP0 to INTP6 to "neither rising nor falling edge detected" or mask the interrupt request. User's Manual U14665EJ4V0UD 169 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. * TRAP instruction format: TRAP vector (where vector is 0 to 1FH) For details of the instruction function, refer to the V850 Series Architecture User's Manual. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). (4) Sets the EP and ID bits of the PSW. (5) Loads the handler address (00000040H or 00000050H) of the software exception routine in the PC, and transfers control. How a software exception is processed is shown below. Figure 7-10. Software Exception Processing TRAP instruction CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC restored PC PSW exception code 1 1 handler address Exception processing Handler address: 00000040H (Vector = 0nH) 00000050H (Vector = 1nH) 170 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 7-11. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during software exception processing, in order to restore the PC and PSW correctly during restoration by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. User's Manual U14665EJ4V0UD 171 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 EP flag The EP flag in the PSW is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Figure 7-12. EP Flag (EP) After reset: 00000020H 31 PSW 0 8 7 6 5 4 3 2 1 S 0 Z NP EP ID SAT CY OV EP 0 1 Exception processing Exception processing is not in progress Exception processing is in progress 7.5 Exception Trap The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850/SF1, an illegal opcode exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap. * Illegal opcode exception: Occurs if the sub opcode field of an instruction to be executed next is not a valid opcode. 7.5.1 Illegal opcode definition An illegal opcode is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to 1111B. Figure 7-13. Illegal Opcode 15 13 12 11 10 54 0 31 27 26 23 22 21 20 17 16 0011 to xxxxx111111xxxxxxxxxx xxxxxxx 1111 x : don't care 172 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR. (4) Sets the EP and ID bits of the PSW. (5) Loads the handler address (00000060H) for the exception trap routine to the PC, and transfers control. How the exception trap is processed is shown below. Figure 7-14. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC restored PC PSW exception code 1 1 00000060H Exception processing User's Manual U14665EJ4V0UD 173 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.3 Restore To restore or return execution from the exception trap, the RETI instruction is used. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW. The processing of the RETI instruction is shown below. Figure 7-15. RETI Instruction Processing RETI instruction 1 PSW. EP 0 1 PSW. NP 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Jump to PC Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during exception trap processing, in order to restore the PC and PSW correctly during restoration by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. 174 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Priority Control 7.6.1 Priorities of interrupts and exceptions Table 7-3. Priorities of Interrupts and Exceptions RESET RESET NMI INT TRAP ILGOP x x x x NMI * INT * TRAP * ILGOP * RESET: Reset NMI: INT: TRAP: *: x: : : Non-maskable interrupt Maskable interrupt Software exception The item on the left ignores the item above. The item on the left is ignored by the item above. The item above is higher than the item on the left in priority. The item on the left is higher than the item above in priority. ILGOP: Illegal opcode exception 7.6.2 Multiple interrupt servicing Multiple interrupt servicing is a function that allows the nesting of interrupts. the original routine will resume once the higher priority interrupt routine is completed. If an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. Multiple interrupt servicing control is performed when interrupts are enabled (ID = 0). Even in an interrupt servicing routine, multiple interrupt control must be performed when interrupts are enabled (ID = 0). If a maskable interrupt or exception is generated during the service program of maskable interrupt or exception, EIPC and EIPSW must be saved. The following example shows the procedure of multiple interrupt servicing. If a higher priority interrupt is generated and acknowledged, it will be allowed to stop the interrupt service routine currently in progress. Execution of User's Manual U14665EJ4V0UD 175 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (enables interrupt acknowledgement) ... ... * DI instruction (disables interrupt acknowledgement) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Acknowledges interrupt such as INTP input. (2) To generate exception in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (enables interrupt acknowledgement) ... * TRAP instruction * Illegal opcode ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Acknowledges exception such as TRAP instruction. Acknowledges exception such as illegal opcode. 176 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Priorities 0 to 7 (0 is the highest) can be programmed for each maskable interrupt request for multiple interrupt processing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxICn) corresponding to each maskable interrupt request. At reset, the interrupt request is masked by the xxMKn bit, and the priority level is set to 7 by the xxPRn0 to xxPRn2 bits. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) Priorities of maskable interrupts (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed. A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed), maskable interrupts are held pending without being acknowledged. User's Manual U14665EJ4V0UD 177 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Response Time The following table describes the interrupt response time (from interrupt request generation to start of interrupt servicing). Figure 7-16. Pipeline Operation at Interrupt Request Acknowledgement 7 to 14 system clocks System clock Interrupt request Instruction 1 Instruction 2 Instruction 3 Interrupt acknowledge operation Instruction (start instruction of interrupt servicing routine) IF ID 4 system clocks EX MEM WB IFX INT1 INT2 INT3 INT4 IF ID EX MEM WB IFX IDX INT1 to INT4: Interrupt acknowledgement processing IFX: IDX: Invalid instruction fetch Invalid instruction decode Interrupt response time (system clock) Conditions Internal interrupt Minimum Maximum 11 18 External interrupt 13 20 Time to eliminate noise (2 system clocks) is also necessary for external interrupts, except when: * * * * In IDLE/STOP mode External bus is accessed Two or more interrupt request non-sample instructions are executed in succession Accessing interrupt control register 7.8 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction. Interrupt request non-sample instruction * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (vs. PSW) 178 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8.1 Interrupt request valid timing following EI instruction When an interrupt request is generated (IF flag = 1) in the status in which interrupts have been disabled by the DI instruction and interrupts are not masked (MK flag = 0), 7 system clocks are required until the interrupt request is acknowledged following execution of the EI instruction (interrupt enable). If the DI instruction (interrupt disable) is executed during the 7 system clocks, the interrupt request is not acknowledged by the CPU. Therefore, instructions equivalent to 7 system clocks must be inserted as the number of instruction execution clocks after executing the EI instruction (interrupt enable). However, securing 7 system clocks is disabled under the following conditions because an interrupt request is not acknowledged even if 7 system clocks are secured. * In IDLE/STOP mode * When interrupt request non-sampling instruction is executed (instruction to manipulate PSW.ID bit) * Access to interrupt request control register (xxICn) The following shows an example of program processing. [Program processing example] DI : : EI NOP NOP NOP NOP JR : LP1 DI LP1 ;(MK flag = 0) ; Interrupt request generated (IF flag = 1) ;EI instruction executed ;1 system clock ;1 system clock ;1 system clock Note ;1 system clock ;3 system clocks (branched to LP1 routine) ;LP1 routine ;After EI instruction executed, executed at the 8th clock by NOP x 4 and JR instructions Note Do not execute the DI instruction (PSW.ID = 1) during this period. Remarks 1. In this example, the DI instruction is executed at the 8th clock after EI instruction execution, so an interrupt request is acknowledged by the CPU and the interrupt is serviced. 2. This timing does not imply that the interrupt servicing routine instruction is executed at the 8th clock after EI instruction. The interrupt servicing routine instruction is executed 4 system clocks after interrupt request acknowledgement by the CPU. 3. This example indicates the case where an interrupt request is generated (IF flag = 1) before the EI instruction is executed. In the case where an interrupt request is generated (IF flag = 1) after the EI instruction is executed, the interrupt request is also not acknowledged by the CPU if interrupts are disabled (PSW.ID = 1) within 7 system clocks after the IF flag is set (1). User's Manual U14665EJ4V0UD 179 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-17. Pipeline Flow and Interrupt Request Generation Timing (a) When DI instruction is executed at 8th system clock after EI instruction execution (interrupt request is acknowledged) EI IF NOP ID IF NOP EX ID IF NOP MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF DI ei signal intrq signal WB MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB intrq signal generated (b) When DI instruction is executed at 7th system clock after EI instruction execution (interrupt request is not acknowledged) EI IF NOP ID IF NOP EX ID IF NOP MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF NOP WB MEM EX ID IF DI ei signal intrq signal WB MEM EX ID IF WB MEM EX ID WB MEM EX WB MEM WB intrq signal not generated 7.9 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer When using the DMA function, execute the DI instruction before performing bit manipulation of the interrupt control register (xxICn) in the EI status and execute the EI instruction after performing manipulation. Alternately, clear (0) the xxIF bit at the start of the interrupt servicing routine. When not using the DMA function, these manipulations are not required. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 180 User's Manual U14665EJ4V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.10 Key Interrupt Function A key interrupt can be generated by inputting a falling edge to the key input pins (KR0 to KR7) by setting the key return mode register (KRM). The key return mode register (KRM) includes 5 bits. The KRM0 bit controls the KR0 to KR3 signals in 4-bit units and the KRM4 to KRM7 bits control corresponding signals from KR4 to KR7 (arbitrary setting from 4 to 8 bits is possible). This register can be read/written in 8-bit or 1-bit units. After reset: 00H 7 R/W 6 KRM6 5 KRM5 Address: FFFFF3D0H 4 KRM4 3 0 2 0 1 0 0 KRM0 KRM KRM7 KRMn 0 1 Key return signal not detected Key return signal detected Key return mode control Caution If the key return mode register (KRM) is changed, an interrupt request flag may be set. To avoid this flag being set, change the KRM register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag. Table 7-4. Description of Key Return Detection Pin Flag KRM0 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 to KR3 signals in 4-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units User's Manual U14665EJ4V0UD 181 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-18. Key Return Block Diagram KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 INTKR KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 Key return mode register (KRM) 182 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.1 16-Bit Timers TM0, TM1, TM7 Remark 8.1.1 Outline * 16-bit capture/compare registers: 2 (CRn0, CRn1) * Independent capture/trigger inputs: 2 (TIn0, TIn1) * Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) * Event input (shared with TIn0) via digital noise eliminator and support of edge specifications * Timer output operated by match detection: 1 each (TOn) When using the P104/TO0, P107/TO1, and P100/TO7 pins as TO0, TO1, and TO7 (timer output), set the value of port 10 (P10) to 0 (port mode output) and the port 10 mode register (PM10) to 0. The logical sum (ORed) value of the output of a port and a timer is output. 8.1.2 Function TM0, TM1, and TM7 have the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square wave output * One-shot pulse output Figure 8-1 shows the block diagram. n = 0, 1, 7 in section 8.1. User's Manual U14665EJ4V0UD 183 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-1. Block Diagram of TM0, TM1, and TM7 Internal bus Capture/compare control register n (CRCn) CRCn2 CRCn1 CRCn0 Selector Noise eliminator Selector INTTMn0 TIn1 16-bit capture/compare register n0 (CRn0) Match Count clock Note Selector 16-bit timer register (TMn) Clear Output controller TOn fxx/2 Noise eliminator Match 3 TIn0 Noise eliminator 16-bit capture/compare register n1 (CRn1) INTTMn1 Selector CRCn2 Prescaler mode register n1 (PRMn1) PRMn2 PRMn1 PRMn0 TMCn3 TMCn2 TMCn1 OVFn OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn 16-bit timer mode control register n (TMCn) Prescaler mode register n0 (PRMn0) Timer output control register n (TOCn) Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. (1) Interval timer Generates an interrupt at preset time intervals. (2) PPG output Can output a square wave with a frequency and output-pulse width that can be set arbitrarily. (3) Pulse width measurement Can measure the pulse width of a signal input from an external source. (4) External event counter Can measure the number of pulses of a signal input from an external source. (5) Square wave output Can output a square wave of any frequency. (6) One-shot pulse output Can output a one-shot pulse with any output pulse width. 184 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.1.3 Configuration Timers 0, 1, and 7 include the following hardware. Table 8-1. Configuration of Timers 0, 1, and 7 Item Timer registers Registers Timer outputs Control registers 16 bits x 3 (TM0, TM1, TM7) Capture/compare registers: 16 bits x 6 (CRn0, CRn1) 3 (TO0, TO1, TO7) 16-bit timer mode control register n (TMCn) Capture/compare control register n (CRCn) 16-bit timer output control register n (TOCn) Prescaler mode registers n0, n1 (PRMn0, PRMn1) Configuration (1) 16-bit timer registers 0, 1, 7 (TM0, TM1, TM7) TMn is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. The count value is reset to 0000H in the following cases: <1> At RESET input <2> If TMCn3 and TMCn2 are cleared <3> If the valid edge of TIn0 is input in the clear & start mode set by inputting the valid edge of TIn0 <4> If TMn and CRn0 match in the clear & start mode set on a match between TMn and CRn0 <5> If OSPTn is set or if the valid edge of TIn0 is input in the one-shot pulse output mode User's Manual U14665EJ4V0UD 185 CHAPTER 8 TIMER/COUNTER FUNCTION (2) Capture/compare register n0 (CR00, CR10, CR70) CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by bit 0 (CRCn0) of the CRCn register. (a) When using CRn0 as compare register The value set to CRn0 is always compared with the count value of the TMn register. When the values of the two match, an interrupt request (INTTMn0) is generated. When TMn is used as an interval timer, CRn0 can also be used as a register that holds the interval time. (b) When using CRn0 as capture register The valid edge of the TIn0 or TIn1 pin can be selected as a capture trigger. The valid edge for TIn0 or TIn1 is set by using the PRMn0 register. When the valid edge for TIn0 pin is specified as the capture trigger, refer to Table 8-2. When the valid edge for TIn1 pin is specified as the capture trigger, refer to Table 8-3. Table 8-2. Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 0 0 1 1 ESn00 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid Edge of TIn0 Pin Rising edge Falling edge Setting prohibited No capture operation CRn0 Capture Trigger Table 8-3. Valid Edge of TIn1 Pin and Capture Trigger of CRn0 ESn11 0 0 1 1 ESn10 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid Edge of TIn1 Pin Falling edge Rising edge Setting prohibited Both rising and falling edges CRn0 Capture Trigger CRn0 is set by a 16-bit memory manipulation instruction. These registers can be read/written when used as compare registers, and can only be read when used as capture registers. RESET input sets this register to 0000H. Caution In the clear & start mode entered on a match between TMn and CRn0, set CRn0 to a value other than 0000H. In the free-running mode or the TIn0 valid edge clear mode, however, an interrupt request (INTTMn0) is generated after an overflow (FFFFH) when CRn0 is set to 0000H. 186 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (3) Capture/compare register n1 (CR01, CR11, CR71) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRCn2) of the CRCn register. (a) When using CRn1 as compare register The value set to CRn1 is always compared with the count value of TMn. When the values of the two match, an interrupt request (INTTMn1) is generated. (b) When using CRn1 as capture register The valid edge of the TIn1 pin can be selected as a capture trigger. The valid edge of TIn1 is specified using the PRMn0 register. When the capture trigger is specified as the valid edge of TIn0, the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows. Table 8-4. TIn0 Pin Valid Edge and CRn1 Capture Trigger ESn01 0 0 1 1 ESn00 0 1 0 1 TIn0 Pin Valid Edge Falling edge Rising Edge Setting prohibited Both rising and falling edges CRn1 Capture Trigger Falling edge Rising Edge Setting prohibited Both rising and falling edges CRn1 is set by a 16-bit memory manipulation instruction. These registers can be read/written when used as compare registers, and can only be read when used as capture registers. RESET input sets this register to 0000H. Caution In the clear & start mode entered on a match between TMn and CRn0, set CRn1 to a value other than 0000H. In the free-running mode or the TIn1 valid edge clear mode, however, an interrupt request (INTTMn1) is generated after an overflow (FFFFH) when 0000H is set to CRn1. User's Manual U14665EJ4V0UD 187 CHAPTER 8 TIMER/COUNTER FUNCTION 8.1.4 Timer 0, 1, 7 control registers The registers to control timers 0, 1, and 7 are shown below. * 16-bit timer mode control register n (TMCn) * Capture/compare control register n (CRCn) * 16-bit timer output control register n (TOCn) * Prescaler mode registers n0, n1 (PRMn0, PRMn1) (1) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn specifies the operation mode of the 16-bit timer, and the clear mode, output timing, and overflow detection of 16-bit timer register n. TMCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears TMC0, TMC1, and TMC7 to 00H. Caution 16-bit timer register n starts operating when TMCn2 and TMCn3 are set to values other than 0, 0 (operation stop mode). To stop the operation, set TMCn2 and TMCn3 to 0, 0. 188 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H R/W 7 TMCn 0 6 0 5 0 4 0 Address: FFFFF208H, FFFFF218H, FFFFF3A8H 3 TMCn3 2 TMCn2 1 TMCn1 0 OVFn TMCn3 0 0 0 TMCn2 0 0 1 TMCn1 0 0 0 Selection operation mode and clear mode Operation stops (TMn is cleared to 0) Free-running mode Selection TOn output timing Not affected Generation of interrupt Not generated Match between TMn and CRn0 or match between TMn and CRn1 Generated on match between TMn and CRn0 and match between TMn and CRn1 0 1 1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 1 0 0 Clears and starts at valid edge of TIn0 Match between TMn and CRn0 or match between TMn and CRn1 1 0 1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 1 1 0 Clears and starts on match between TMn and CRn0 Match between TMn and CRn0 or match between TMn and CRn1 Match between TMn and CRn0, match between TMn and CRn1, or valid edge of TIn0 1 1 1 OVFn 0 1 Did not overflow Overflow occurred Detection of overflow of 16-bit timer register n Cautions 1. When a bit other than the OVFn flag is written, be sure to stop the timer operation. 2. The valid edge of the TIn0 pin is set by using prescaler mode register n0 (PRMn0). 3. When a mode in which the timer is cleared and started on a match between TMn and CRn0 is selected, the OVFn flag is set to 1 when the count value of TMn changes from FFFFH to 0000H with CRn0 set to FFFFH. 4. Remark Be sure to set bits 7 to 4 to 0. Output pin of timer n Input pin of timer n 16-bit timer register n TOn: TIn0: TMn: CRn0: Compare register n0 CRn1: Compare register n1 User's Manual U14665EJ4V0UD 189 CHAPTER 8 TIMER/COUNTER FUNCTION (2) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn controls the operation of capture/compare register n (CRn0 and CRn1). CRCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0, CRC1, and CRC7 to 00H. After reset: 00H R/W 7 CRCn 0 6 0 Address: FFFFF20AH, FFFFF21AH, FFFFF3AAH 5 0 4 0 3 0 2 CRCn2 1 CRCn1 0 CRCn0 CRCn2 0 1 Selection of operation mode of CRn1 Operates as compare register Operates as capture register CRCn1 0 1 Selection of capture trigger of CRn0 Captured at valid edge of TIn1 Captured in reverse phase of valid edge of TIn0 CRCn0 0 1 Selection of operation mode of CRn0 Operates as compare register Operates as capture register Cautions 1. Before setting CRCn, be sure to stop the timer operation. 2. When the mode in which the timer is cleared and started on a match between TMn and CRn0 is selected by 16-bit timer mode control register n (TMCn), do not specify CRn0 as a capture register. 3. When both the rising edge and falling edge are specified for the TIn0 valid edge, the capture operation does not work. 4. For the capture trigger, a pulse longer than twice the count clock selected by prescaler mode registers 0n, 1n (PRM0n, PRM1n) is required for the signals from TIn0 and T2n1 to perform the capture operation correctly. 5. Be sure to set bits 7 to 3 to 0. 190 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (3) 16-bit timer output control registers 0, 1, 7 (TOC0, TOC1, TOC7) TOCn controls the operation of the timer n output controller by setting or resetting the R-S flip-flop (LV0), enabling or disabling inverse output, enabling or disabling output of timer n, enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. TOCn is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears TOC0, TOC1, and TOC7 to 00H. User's Manual U14665EJ4V0UD 191 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H R/W 7 TOCn 0 6 OSPTn Address: FFFFF20CH, FFFFF21CH, FFFFF3ACH 5 OSPEn 4 TOCn4 3 LVSn 2 LVRn 1 TOCn1 0 TOEn OSPTn 0 1 Control of output trigger of one-shot pulse by software No one-shot pulse trigger One-shot pulse trigger used OSPEn 0 1 Control of one-shot pulse output operation Successive pulse output One-shot pulse output Note TOCn4 0 1 Control of timer output F/F on match between CRn1 and TMn Inverse timer output F/F disabled Inverse timer output F/F enabled LVSn 0 0 1 1 LVRn 0 1 0 1 Not affected Status setting of timer output F/F of timer n Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TOCn1 0 1 Control of timer output F/F on match between CRn0 and TMn or TIn0 valid edge Inverse timer output F/F disabled Inverse timer output F/F enabled TOEn 0 1 Control of output of timer n Output disabled (output is fixed to 0 level) Output enabled Note The one-shot pulse output operates only in the free-running mode and in the clear & start mode entered upon detection of the TIn0 valid edge. Cautions 1. Before setting TOCn, be sure to stop the timer operation. 2. LVSn and LVRn are 0 when read after data has been set to them. 3. OSPTn is 0 when read because it is automatically cleared after data has been set. 4. Do not set OSPTn (to 1) for other than one-shot pulse output. 192 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (4) Prescaler mode registers 00, 01 (PRM00, PRM01) PRM00 and PRM01 select the count clock of the 16-bit timer (TM0) and the valid edge of TI00 or TI01 input. PRM00 and PRM01 are set by an 8-bit memory manipulation instruction. RESET input clears PRM00 and PRM01 to 00H. After reset: 00H R/W 7 PRM00 ES011 6 ES010 Address: FFFFF206H 5 ES001 4 ES000 3 0 2 0 1 PRM01 0 PRM00 After reset: 00H R/W 7 PRM01 0 6 0 Address: FFFFF20EH 5 0 4 0 3 0 2 0 1 0 0 PRM02 ES011 0 0 1 1 ES010 0 1 0 1 Falling edge Rising edge Setting prohibited Selection of valid edge of TI01 Both rising and falling edges ES001 0 0 1 1 ES000 0 1 0 1 Falling edge Rising edge Setting prohibited Selection of valid edge of TI00 Both rising and falling edges Count clock selection PRM02 PRM01 PRM00 Count clock 16 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/16 INTWTNI TI00 valid edge fXX/4 fXX/64 fXX/256 Setting prohibited Note fXX 8 MHz 250 ns 2 s - - 250 ns 4 s 16 s - 8 s 32 s - - - 500 ns 125 ns 1 s Note An external clock requires a pulse longer than twice the internal clock (fXX/2). User's Manual U14665EJ4V0UD 193 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TI00 as the count clock, do not specify the valid edge of TI00 to clear and start the timer and as a capture trigger. 2. Before setting data to PRM00 and PRM01, be sure to stop the timer operation. 3. If the 16-bit timer (TM0) operation is enabled by specifying the rising edge or both edges as the valid edge of the TI00 or TI01 pin while the TI00 or TI01 pin is high level immediately after system reset, the rising edge is detected immediately after specification of the rising edge or both edges. Care is therefore needed when pulling up the TI00 or TI01 pin. However, the rising edge is not detected when operation is enabled after it has been stopped. 194 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (5) Prescaler mode registers m0, m1 (PRMm0, PRMm1) PRMm0 and PRMm1 select the count clock of the 16-bit timer (TM1, TM7) and the valid edge of the TIm0, TIm1 input. PRMm0 and PRMm1 are set by an 8-bit memory manipulation instruction (m = 1, 7). RESET input clears PRMm0 and PRMm1 to 00H. After reset: 00H R/W 7 PRMm0 ESm11 6 ESm10 Address: FFFFF216H, FFFFF3A6H 5 ESm01 4 ESm00 3 0 2 0 1 PRMm1 0 PRMm0 After reset: 00H R/W 7 PRMm1 0 6 0 Address: FFFFF21EH, FFFFF3AEH 5 0 4 0 3 0 2 0 1 0 0 PRMm2 ESm11 0 0 1 1 ESm10 0 1 0 1 Falling edge Rising edge Setting prohibited Selection of valid edge of TIm1 Both rising and falling edges ESm01 0 0 1 1 ESm00 0 1 0 1 Falling edge Rising edge Setting prohibited Selection of valid edge of TIm0 Both rising and falling edges Count clock selection PRMm2 PRMm1 PRMm0 Count clock 16 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/4 fXX/16 TIm0 valid edge fXX/32 fXX/128 fXX/256 Setting prohibited Note fXX 8 MHz 250 ns 500 ns 2 s - 2 s 8 s 16 s - 4 s 16 s 32 s - - 125 ns 250 ns 1 s Note An external clock requires a pulse longer than twice the internal clock (fXX/2). User's Manual U14665EJ4V0UD 195 CHAPTER 8 TIMER/COUNTER FUNCTION Cautions 1. When selecting the valid edge of TIm0 as the count clock, do not specify the valid edge of TIm0 to clear and start the timer and as a capture trigger. 2. Before setting data to PRMm0, PRMm1, be sure to stop the timer operation. 3. If the 16-bit timer (TM1, TM7) operation is enabled by specifying the rising edge or both edges for the valid edge of the TIm0, TIm1 pin while the TIm0, TIm1 pin is high level immediately after system reset, the rising edge is detected immediately after specification of the rising edge or both edges. Care is therefore needed when pulling up the TIm0, TIm1 pin. However, the rising edge is not detected when operation is enabled after it has been stopped. Remark m = 1, 7 196 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.2 Operation of 16-Bit Timers TM0, TM1, TM7 Remark n = 0, 1, 7 in section 8.2. 8.2.1 Operation as interval timer TMn operates as an interval timer when 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) are set as shown in Figure 8-2. In this case, TMn repeatedly generates an interrupt at the time interval specified by the count value preset to 16-bit capture/compare register n0 (CRn0). When the count value of TMn matches the set value of CRn0, the value of TMn is cleared to 0, and the timer continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. The count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (PRMn0 and PRMn1) of prescaler mode register n0 (PRMn0) and by bits 0 (PRMn2) of prescaler mode register n1 (PRMn1). Figure 8-2. Control Register Settings When TMn Operates as Interval Timer (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0/1 OVFn 0 Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 0 CRn0 used as compare register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the interval timer function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. User's Manual U14665EJ4V0UD 197 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-3. Configuration of Interval Timer 16-bit capture/compare register n0 (CRn0) INTTMn0 Count clock TIn0 Note Selector Noise eliminator 16-bit timer register n (TMn) OVFn Clear circuit fXX/2 Note The count clock is set by the PRMn0 and PRMn1 registers. Remark " " indicates a signal that can be directly connected to a port. Figure 8-4. Timing of Interval Timer Operation t Count clock TMn count value 0000H 0001H N 0000H 0001H N 0000H 0001H N Count start CRn0 INTTMn0 N Clear N Clear N N Interrupt acknowledgement TOn Interval time Interval time Interrupt acknowledgement Interval time Remark Interval time = (N + 1) x t: N = 0001H to FFFFH 198 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.2 PPG output operation TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n (TMCn) and capture/compare control register n (CRCn) as shown in Figure 8-5. The PPG output function outputs a square wave from the TOn pin with a cycle specified by the count value preset to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value preset to 16-bit capture/compare register n1 (CRn1). Figure 8-5. Control Register Settings in PPG Output Operation (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0 OVFn 0 Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0 CRCn1 x CRCn0 0 x : don't care CRn0 used as compare register CRn1 used as compare register (c) 16-bit timer output control registers 0, 1, 7 (TOC0, TOC1, TOC7) OSPTn TOCn 0 0 OSPEn 0 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1 Enables TOn output. Reverses output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Reverses output on match between TMn and CRn1. Disables one-shot pulse output. Cautions 1. Make sure that CRn0 and CRn1 are set to 0000H < CRn1 < CRn0 FFFFH. 2. PPG output sets the pulse cycle to (CRn0 setup value + 1). The duty factor is (CRn1 setup value + 1)/(CRn0 setup value + 1). User's Manual U14665EJ4V0UD 199 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-6. Configuration of PPG Output 16-bit capture/compare register n0 (CRn0) Selector Count clockNote TIn0 Noise eliminator fxx/2 16-bit timer register n (TMn) Clear circuit Output controller TOn 16-bit capture/compare register n1 (CRn1) Note The count clock is set by the PRMn0 and PRMn1 registers. Remark " " indicates a signal that can be directly connected to a port. Figure 8-7. PPG Output Operation Timing t Count clock TMn count value 0000H 0001H Count starts Value loaded to CRn0 Value loaded to CRn1 TOn Pulse width: M x t 1 cycle: N x t N M M-1 M N-1 N 0000H 0001H Clear Remark 0000H < M < N FFFFH 200 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.3 Pulse width measurement 16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1 pins. Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TIn0 pin. (1) Pulse width measurement with free-running counter and one capture register If the edge specified by prescaler mode register n0 (PRMn0) is input to the TIn0 pin when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 8-8), the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set. The edge is specified using bits 6 and 7 (ESn10 and ESn11) of prescaler mode register n0 (PRMn0). The rising edge, falling edge, or both edges can be selected. The valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (PRMn0, PRMn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. Figure 8-8. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0 Free-running mode (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 1 CRCn1 0/1 CRCn0 0 CRn0 used as compare register CRn1 used as capture register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. User's Manual U14665EJ4V0UD 201 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-9. Configuration for Pulse Width Measurement with Free-Running Counter Count clock Note Selector 16-bit timer register n (TMn) OVFn TIn0 16-bit capture/compare register n1 (CRn1) INTTMn1 Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. Remark " " indicates a signal that can be directly connected a port. Figure 8-10. Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TMn count value TIn0 pin input Value loaded to CRn1 INTTMn1 D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 OVFn (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t 202 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 8-11). When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1) and an external interrupt request signal (INTTMn1) is set. When the edge specified by bits 6 and 7 (ESn10 and ESn11) of PRMn0 is input to the TIn1 pin, the value of TMn is loaded to 16-bit capture/compare register n0 (CRn0), and an external interrupt request signal (INTTMn0) is set. The edges of the TIn0 and TIn1 pins are specified by bits 4 and 5 (ESn00 and ESn01) and bits 6 and 7 (ESn10 and ESn11) of PRMn0, respectively. The rising, falling, or both rising and falling edges can be specified. The valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (PRMn0, PRMn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. Figure 8-11. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0 Free-running mode (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 1 CRCn1 0 CRCn0 1 CRn0 as capture register Captures valid edge of TIn1 pin to CRn0. CRn1 as capture register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. User's Manual U14665EJ4V0UD 203 CHAPTER 8 TIMER/COUNTER FUNCTION * Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 8-12. CRn1 Capture Operation with Rising Edge Specified Count clock TMn TIn0 Rising edge detection CRn1 INTTMn1 N N-3 N-2 N-1 N N+1 Figure 8-13. Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified) t Count clock TMn count value TIn0 pin input Value loaded to CRn1 INTTMn1 TIn1 pin input Value loaded to CRn0 INTTMn0 OVFn (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1) x t (D3 - D2) x t D1 D2+1 D0 D1 D2 0000H 0001H D0 D0+1 D1 D1+1 FFFFH 0000H D2 D2+1 D2+2 D3 204 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer register n (TMn) is used as a free-running counter (refer to Figure 8-14), the pulse width of the signal input to the TIn0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0) is input to the TIn0 pin, the value of TMn is loaded to 16-bit capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set. The value of TMn is also loaded to 16-bit capture/compare register n0 (CRn0) when an edge that is the reverse of the one that triggers capturing to CRn1 is input. The edge of the TIn0 pin is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0). The rising or falling edge can be specified. The valid edge of TIn0 is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (PRMn0, PRMn1), and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges, capture/compare register n0 (CRn0) cannot perform a capture operation. Figure 8-14. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0/1 OVFn 0 Free-running mode (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 1 CRCn1 1 CRCn0 1 CRn0 used as capture register Captures to CRn0 at edge reverse to valid edge of TIn0 pin. CRn1 used as capture register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. User's Manual U14665EJ4V0UD 205 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TMn count value TIn0 pin input Value loaded to CRn1 Value loaded to CRn0 INTTMn1 OVFn (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D2 0000H 0001H D0 D0+1 D1 D1+1 FFFFH 0000H D2 D2+1 D3 D1 D3 (4) Pulse width measurement by restarting When the valid edge of the TIn0 pin is detected, the pulse width of the signal input to the TIn0 pin can be measured by clearing 16-bit timer register n (TMn) once and then resuming counting after loading the count value of TMn to 16-bit capture/compare register n1 (CRn1). (See Figure 8-17) The edge is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0). The rising or falling edge can be specified. The valid edge is detected by sampling with a count clock cycle selected by prescaler mode register n0 and n1 (PRMn0, PRMn1) and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges, capture/compare register n0 (CRn0) cannot perform a capture operation. 206 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 0 TMCn1 0/1 OVFn 0 Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 1 CRCn1 1 CRCn0 1 CRn0 used as capture register Captures to CRn0 at edge reverse to valid edge of TIn0. CRn1 used as capture register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse width measurement function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. Figure 8-17. Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) t Count clock TMn count value TIn0 pin input Value loaded to CRn1 Value loaded to CRn0 INTTMn1 (D1+1) x t (D2+1) x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H User's Manual U14665EJ4V0UD 207 CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.4 Operation as external event counter TMn can be used as an external event counter that counts the number of clock pulses input to the TIn0 pin from an external source by using 16-bit timer register n (TMn). Each time the valid edge specified by prescaler mode register n0 (PRMn0) has been input, TMn is incremented. When the count value of TMn matches the value of 16-bit capture/compare register n0 (CRn0), TMn is cleared to 0, and an interrupt request signal (INTTMn0) is generated. The edge is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0). The rising, falling, or both the rising and falling edges can be specified. The valid edge is detected by sampling with a count clock cycle of fxx/2, and the capture operation is not performed until the valid level is detected two times, eliminating noise with a short pulse width. Figure 8-18. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0/1 OVFn 0 Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 0 CRn0 used as compare register Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the external event counter function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. 208 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-19. Configuration of External Event Counter 16-bit capture/compare register n0 (CRn0) Match Clear Count clockNote Selector 16-bit timer/counter n (TMn) OVFn INTTMn0 fxx/2 Valid edge of TIn0 Noise eliminator 16-bit capture/compare register n1 (CRn1) Internal bus Note The count clock is set by the PRMn0 and PRMn1 registers. Remark " " indicates a signal that can be directly connected to a port. Figure 8-20. Timing of External Event Counter Operation (with Rising Edge Specified) TIn0 pin input TMn count value CRn0 INTTMn0 0000H 0001H 0002H 0003H 0004H 0005H N-1 N 0000H 0001H 0002H 0003H N Caution Read TMn when reading the count value of the external event counter. 8.2.5 Operation as square-wave output TMn can be used to output a square wave with any frequency at an interval specified by the count value preset to 16-bit capture/compare register n0 (CRn0). By setting bits 0 (TOEn) and 1 (TOCn1) of 16-bit timer output control register n (TOCn) to 1, the output status of the TOn pin is reversed at an interval specified by the count value preset to CRn1. In this way, a square wave of any frequency can be output. User's Manual U14665EJ4V0UD 209 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-21. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 1 TMCn1 0 OVFn 0 Clears and starts on match between TMn and CRn0. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0/1 CRCn1 0/1 CRCn0 0 CRn0 used as compare register (c) 16-bit timer output control registers 0, 1, 7 (TOC0, TOC1, TOC7) OSPTn TOCn 0 0 OSPEn 0 TOCn4 0 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1 Enables TOn output. Inverts output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Does not invert output on match between TMn and CRn1. Disables one-shot pulse output. Remark 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. 210 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-22. Timing of Square-Wave Output Operation Count clock TMn count value CRn0 INTTMn0 TOn pin output 0000H 0001H 0002H N-1 N 0000H 0001H 0002H N-1 N 0000H N 8.2.6 Operation as one-shot pulse output TMn can output a one-shot pulse in synchronization with a software trigger and an external trigger (TIn0 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TOn pin by setting 16-bit timer mode control register n (TMCn), capture/compare control register n (CRCn), and 16-bit timer output control register n (TOCn) as shown in Figure 8-23, and by setting bit 6 (OSPTn) of TOCn by software. By setting OSPTn to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted at the count value (N) preset to 16-bit capture/compare register n1 (CRn1). After that, the output is deasserted at the count value (M) preset to 16-bit capture/compare register n0 (CRn0)Note. Even after a one-shot pulse has been output, TMn continues its operation. To stop TMn, TMCn must be reset to 00H. Note This is an example when N < M. When N > M, the output becomes active at the CRn0 value and inactive at the CRn1 value. Caution Do not set OSPTn to 1 while a one-shot pulse is being output. To output a one-shot pulse again, wait until the current one-shot pulse output ends. User's Manual U14665EJ4V0UD 211 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 0 TMCn2 1 TMCn1 0 OVFn 0 Free-running mode (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0 CRCn1 0/1 CRCn0 0 CRn0 used as compare register CRn1 used as compare register (c) 16-bit timer output control registers 0, 1, 7 (TOC0, TOC1, TOC7) OSPTn TOCn 0 0 OSPEn 1 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1 Enables TOn output. Inverts output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Inverts output on match between TMn and CRn1. Sets one-shot pulse output mode. Set to 1 for output. Caution Remark Do not set CRn0 and CRn1 to 0000H. 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. 212 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-24. Timing of One-Shot Pulse Output Operation with Software Trigger Sets 0CH to TMCn (TMn count starts) Count clock TMn count value CRn1 set value CRn0 set value OSPTn INTTMn1 INTTMn0 TOn pin output 0000H 0001H N N+1 0000H N-1 N M-1 M M+1 M+2 N N N N M M M M Caution 16-bit timer register n starts operating as soon as TMCn2 and TMCn3 are set to values other than 0, 0 (operation stop mode). Remark N User's Manual U14665EJ4V0UD 213 CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-25. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) TMCn3 TMCn 0 0 0 0 1 TMCn2 0 TMCn1 0 OVFn 0 Clears and starts at valid edge of TIn0 pin. (b) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) CRCn2 CRCn 0 0 0 0 0 0 CRCn1 0/1 CRCn0 0 CRn0 used as compare register CRn1 used as compare register (c) 16-bit timer output control registers 0, 1, 7 (TOC0, TOC1, TOC7) OSPTn TOCn 0 0 OSPEn 1 TOCn4 1 LVSn 0/1 LVRn 0/1 TOCn1 1 TOEn 1 Enables TOn output. Inverts output on match between TMn and CRn0. Specifies initial value of TOn output F/F. Inverts output on match between TMn and CRn1. Sets one-shot pulse output mode. Caution Remark Do not clear CRn0 and CRn1 to 0000H. 0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the square-wave output function. For details, refer to 8.1.4 Timer 0, 1, 7 control registers. 214 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Sets 08H to TMCn (TMn count starts) Count clock TMn count value Value to set CRn1 Value to set CRn0 TIn0 pin input INTTMn1 INTTMn0 TOn pin output 0000H 0001H 0000H N N+1 N+2 M-2 M-1 M M+1 M+2 N N N N M M M M Caution The 16-bit timer register starts operating as soon as TMCn2 and TMCn3 are set to values other than 0, 0 (operation stop mode). User's Manual U14665EJ4V0UD 215 CHAPTER 8 TIMER/COUNTER FUNCTION 8.2.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer register n (TMn) is started asynchronously to the count pulse. Figure 8-27. Start Timing of 16-Bit Timer Register n Count pulse TMn count value 0000H Timer starts 0001H 0002H 0003H 0004H (2) 16-bit capture/compare register setting (in the clear & start mode entered on match between TMn and CRn0) Set 16-bit capture/compare registers n0, n1 (CRn0, CRn1) to a value other than 0000H (a 1-pulse count operation is disabled when these registers are used as event counters). (3) Setting compare register during timer count operation If the value to which the current value of 16-bit capture/compare register n0 (CRn0) has been changed is less than the value of 16-bit timer register n (TMn), TMn continues counting, overflows, and starts counting again from 0. If the new value of CRn0 (M) is less than the old value (N), the timer must be restarted after the value of CRn0 has been changed. Figure 8-28. Timing After Changing Compare Register During Timer Count Operation Count pulse CRn0 TMn count value N X-1 X M FFFFH 0000H 0001H 0002H Remark N>X>M 216 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (4) Data hold timing of capture register If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is read, CRn1 performs a capture operation, but this capture value is not guaranteed. However, the interrupt request signal (INTTMn1) is set as a result of detection of the valid edge. Figure 8-29. Data Hold Timing of Capture Register Count pulse TMn count value Edge input INTTMn1 Capture read signal CRn1 interrupt value X Capture operation N+1 Capture operation is performed but it is not guaranteed. N N+1 N+2 M M+1 M+2 (5) Setting valid edge Before setting the valid edge of the TIn0 pin, stop the timer operation by resetting bits 2 and 3 (TMCn2 and TMCn3) of 16-bit timer mode control register n to 0, 0. Set the valid edge by using bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0). (6) Re-triggering one-shot pulse (a) One-shot pulse output via software When a one-shot pulse is output, do not set OSPTn to 1. Do not output the one-shot pulse again until the current one-shot pulse output ends. (b) One-shot pulse output via external trigger Even if the external trigger is generated again while a one-shot pulse is being output, it is ignored. (c) One-shot pulse output function When using a software trigger for one-shot pulse output of timers 0, 1, and 7, the level of the TIn0 pin or its alternate-function pin cannot be changed. The reason for this is that the timer is inadvertently cleared and started at the level of the TIn0 pin or its alternate-function pin and pulses are output at an unintended timing because the external trigger is valid. User's Manual U14665EJ4V0UD 217 CHAPTER 8 TIMER/COUNTER FUNCTION (7) Operation of OVFn flag (a) OVFn flag set The OVFn flag is set to 1 in the following case in addition to when an overflow of the TMn register occurs: Selection of mode in which TM0 is cleared and started on match between TMn and CRn0. CRn0 set to FFFFH When TMn is cleared from FFFFH to 0000H by a match with CRn0. Figure 8-30. Operation Timing of OVFn Flag Count pulse CRn0 TMn OVFn INTTMn0 FFFFH FFFEH FFFFH 0000H 0001H (b) Clear OVFn flag Even if the OVFn flag is cleared before the next count clock is counted (before TMn becomes 0001H) after TMn has overflowed, the OVFn flag is set again and the clear becomes invalid. (8) Conflicting operations (a) If the read period and capture trigger input conflict When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, if the read period and capture trigger input conflict, the capture trigger has priority. The read data of CRn0 and CRn1 is undefined. (b) If the match timings of the write period and TMn conflict When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, because match detection cannot be performed correctly if the match timings of the write period and 16-bit timer register n (TMn) conflict, do not write to CRn0 and CRn1 close to the match timing. 218 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (9) Timer operation (a) CRn1 capture Even if 16-bit timer register n (TMn) is read, a capture to 16-bit capture/compare register n1 (CRn1) is not performed. (b) Acknowledgement of TIn0 and TIn1 pins When the timer is stopped, input signals to the TIn0 and TIn1 pins are not acknowledged, regardless of the CPU operation. (c) One-shot pulse output The one-shot pulse output operates correctly only in free-running mode or in clear & start mode set at the valid edge of the TIn0 pin. A one-shot pulse cannot be output in the clear & start mode set on a match of TMn and CRn0 because an overflow does not occur. (10) Capture operation (a) If the valid edge of TIn0 is specified for the count clock When the valid edge of TIn0 is specified for the count clock, the capture register with TIn0 specified as a trigger will not operate correctly. (b) If both rising and falling edges are selected as the valid edge of TIn0 If both rising and falling edges are selected as the valid edge of TIn0, a capture operation is not performed. (c) To capture the signals correctly from TIn0 and TIn1 The capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 (PRMn0, PRMn1) in order to correctly capture the signals from TIn1 and TIn0. (d) Interrupt request input Although a capture operation is performed at the falling edge of the count clock, interrupt request inputs (INTTMn0, INTTMn1) are generated at the rising edge of the next count clock. (11) Compare operation (a) When rewriting CRn0 and CRn1 during timer operation When rewriting 16-bit timer capture/compare registers n0 and n1 (CRn0, CRn1), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) When CRn0 and CRn1 are set to compare mode When CRn0 and CRn1 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. User's Manual U14665EJ4V0UD 219 CHAPTER 8 TIMER/COUNTER FUNCTION (12) Edge detection (a) When the TIn0 or TIn1 pin is high level immediately after a system reset When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n (TMn) is then enabled, the rising edge will be detected immediately. Care is therefore needed when the TIn0 or TIn1 pin is pulled up. However, when operation is enabled after being stopped, the rising or falling edge is not detected. (b) Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the TIn0 valid edge is used as a count clock or a capture trigger. The former is sampled by fxx/2, and the latter is sampled by the count clock selected using prescaler mode registers n0 or n1 (PRMn0, PRMn1). Detecting the valid edge can eliminate short pulse width noise because a capture operation is performed only after the valid edge is sampled and a valid level is detected twice. 220 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.3 16-Bit Timers TM2 to TM6 Remark n = 2 to 6 in section 8.3. 8.3.1 Functions TM2 to TM5 have the following functions. * PWM output with 16-bit resolution * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square-wave output with 16-bit resolution TM6 has the following function. * Interval timer with 16-bit resolution Figure 8-31. Block Diagram of TM2 to TM6 Internal bus 16-bit compare register n (CRn) Match TIm Count clock Note 1 Selector Mask circuit S Q INV R INTTMn Note 2 Selector 16-bit counter OVF n (TMn) Clear Selector TOm 4 S Selector R Q Invert level TCLn3 TCLn2 TCLn1 TCLn0 TCEn0 TMCn06 0 LVSm0 LVRm0 TMCm01 TOEm0 Timer clock selection register n0, n1 (TCLn0, TCLn1) Timer mode control register n (TMCn0) Internal bus Notes 1. The count clock is set by the TCLn register. 2. Serial interface clock (TM2 and TM3 only) Remarks 1. " ]" is a signal that can be directly connected to a port. 2. m = 2 to 5 User's Manual U14665EJ4V0UD 221 CHAPTER 8 TIMER/COUNTER FUNCTION 8.3.2 Configuration Timer n includes from the following hardware. Table 8-5. Configuration of Timers 2 to 6 Item Timer registers Registers Timer outputs Control registers 16-bit counters 2 to 6 (TM2 to TM6) 16-bit compare registers 2 to 6 (CR2 to CR6) TO2 to TO5 Timer clock selection registers 20 to 60 and 21 to 61 (TCL20 to TCL60 and TCL21 to TCL61) 16-bit timer mode control registers 20 to 60 (TMC20 to TMC60) Configuration (1) 16-bit counters 2 to 6 (TM2 to TM6) TMn is a 16-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. When the count is read out during operation, the count clock input temporarily stops and the count is read at that time. In the following cases, the count becomes 0000H. (1) RESET is input. (2) TCEn is cleared. (3) TMn and CRn match in the clear and start mode that occurs when TMn and CRn0 match. (2) 16-bit compare registers 2 to 6 (CR2 to CR6) The value set in CRn is always compared to the count in 16-bit counter n (TMn). If the two values match, an interrupt request (INTTMn) is generated (except in the PWM mode). Caution Stop the 16-bit timer count operation before changing the set value of 16-bit compare registers 2 to 6 (CR2 to CR6). 222 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.3.3 Timer n control register The following two types of registers control timer n. * Timer clock selection registers n0, n1 (TCLn0, TCLn1) * 16-bit timer mode control register n (TMCn) (1) Timer clock selection registers 20 to 60 and 21 to 61 (TCL20 to TCL60 and TCL21 to TCL61) These registers set the count clock of timer n. TCLn0 and TCLn1 are set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset: 00H R/W 7 TCLm0 (m = 2, 3) 0 6 0 Address: FFFFF244H, FFFFF0E4H 5 0 4 0 3 0 2 TCLm2 1 TCLm1 0 TCLm0 After reset: 00H R/W 7 TCLm1 (m = 2, 3) 0 6 0 Address: FFFFF24EH, FFFFF2EEH 5 0 4 0 3 0 2 0 1 0 0 TCLm3 Count cock selection TCLm3 TCLm2 TCLm1 TCLm0 Count clock 16 MHz 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TIm falling edge TIm rising edge fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXX/512 Setting prohibited Setting prohibited fXX/64 fXX/256 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 4 s 16 s - - - - - - fXX 8 MHz - - 250 ns 500 ns 1 s 2 s 8 s 32 s - - 500 ns 1 s 2 s 4 s 16 s 64 s - - 8 s 32 s - - - - Cautions 1. When TCLm0 and TCLm1 are overwritten by different data, write after temporarily stopping the timer. 2. Be sure to set bits 3 to 7 to in TCLm0 to 0, and bits 1 to 7 in TCLm1 to 0. User's Manual U14665EJ4V0UD 223 CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H R/W 7 TCLm0 (m = 4, 5) 0 6 0 Address: FFFFF264H, FFFFF334H 5 0 4 0 3 0 2 TCLm2 1 TCLm1 0 TCLm0 After reset: 00H R/W 7 TCLm1 (m = 4, 5) 0 6 0 Address: FFFFF26EH, FFFFF33EH 5 0 4 0 3 0 2 0 1 0 0 TCLm3 Count clock selection TCLm3 TCLm2 TCLm1 TCLm0 Count clock 16 MHz 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TIm falling edge TIm rising edge fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXT (subclock) Setting prohibited Setting prohibited fXX/64 fXX/256 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 4 s 16 s - - - - - - fXX 8 MHz - - 250 ns 500 ns 1 s 2 s 8 s 30.5 s - - 500 ns 1 s 2 s 4 s 16 s 30.5 s - - 8 s 32 s - - - - Cautions 1. When TCLm0 and TCLm1 are overwritten by different data, write after temporarily stopping the timer. 2. Be sure to set bits 3 to 7 of TCLm0 and bits 1 to 7 of TCLm1 to 0. 224 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 00H R/W 7 TCL60 0 6 0 Address: FFFFF284H 5 0 4 0 3 0 2 TCL62 1 TCL61 0 TCL60 After reset: 00H R/W 7 TCL61 0 6 0 Address: FFFFF28EH 5 0 4 0 3 0 2 0 1 0 0 TCL63 Count clock selection TCL63 TCL62 TCL61 TCL60 Count clock 16 MHz 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Setting prohibited Setting prohibited fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Setting prohibited Setting prohibited fXX/256 fXX/512 Setting prohibited Setting prohibited Setting prohibited TM0 overflow signal 16 s 32 s - - - - - - fXX 8 MHz - - 250 ns 500 ns 1 s 2 s 4 s 8 s - - 500 ns 1 s 2 s 4 s 8 s 16 s - - 32 s 64 s - - - - Cautions 1. When TCL60 and TCL61 are overwritten by different data, write after temporarily stopping the timer. 2. Be sure to set bits 3 to 7 of TCL60 and bits 1 to 7 of TCL61 to 0. User's Manual U14665EJ4V0UD 225 CHAPTER 8 TIMER/COUNTER FUNCTION (2) 16-bit timer mode control registers 20 to 60 (TMC20 to TMC60) The TMCn0 register makes the following five settings. (1) Controls the counting by 16-bit counter n (TMn) (2) Selects the operation mode of 16-bit counter n (TMn) (3) Sets the state of the timer output flip-flop (4) Controls the timer flip-flop or selects the active level in the PWM (free-running) mode (5) Controls timer output TMCn0 is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 04H (although the state of hardware is initialized to 04H, 00H is read when reading). 226 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION After reset: 04H R/W Address: TMC20 FFFFF246H TMC50 TMC60 FFFFF336H FFFFF286H TMC30 FFFFF0E6H TMC40 FFFFF266H 7 TMCn0 (m = 2 to 6) TCEn0 0 1 TMn count operation control TCEn0 6 TMCn06 5 0 4 0 3 LVSm0 2 1 TMCm01 0 TOEm0 LVRm0 Counting is disabled after the counter is cleared to 0 (prescaler disabled) Start count operation TMCn06 0 1 TMn operating mode selection Clear & start mode when TMn and CRn match PWM (free-running) mode LVSm0 0 0 1 1 LVRm0 0 1 0 1 Not change Setting state of timer output flip-flop Reset timer output flip-flop to 0 Set timer output flip-flop to 1 Setting prohibited TMCm01 Other than PWM (free-running) mode (TMCn06 = 0) Controls timer F/F PWM (free-running) mode (TMCn06 = 1) Selects active level Active high Active low 0 1 Inversion operation disabled Inversion operation enabled TOEm0 0 1 Output disabled (port mode) Output enabled Timer output control Cautions 1. When using as the timer output pin (TOm), set the port value to 0 (port mode output). A logical sum (ORed) value of the timer output value is output. 2. Since TOm and TIm are the same alternate-function pin, only one function can be used. Remarks 1. In the PWM mode, the PWM output is set to the inactive level by TCEm0 = 0. 2. If LVSm0 and LVRm0 are read after setting data, 0 is read. User's Manual U14665EJ4V0UD 227 CHAPTER 8 TIMER/COUNTER FUNCTION 8.4 16-Bit Timer (TM2 to TM6) Operation Remark n = 2 to 6 and m = 2 to 5 in section 8.4. 8.4.1 Operation as interval timer The timer operates as an interval timer that repeatedly generates interrupts at the interval specified by the count value preset to 16-bit compare register n (CRn). If the count value of 16-bit counter n (TMn) matches the set value of CRn, the value of TMn is cleared to 0 and the timer continues counting, and an interrupt request signal (INTTMn) is generated. The TMn count clock can be selected by bits 0 to 2 (TCLn0 to TCLn2) of timer clock selection register n0 (TCLn0) and by bit 0 (TCLn3) of timer clock selection register n1 (TCLn1). Setting method (1) Set each register. * TCLn0, TCLn1: * CRn: * TMCn0: Select the count clock. Compare value Selects the clear and start mode when TMn and CRn match. (TMCn0 = 0000xxx0B, x = don't care) (2) When TCEn0 = 1 is set, counting starts. (3) When the values of TMn and CRn match, INTTMn is generated (TMn is cleared to 0000H). (4) INTTMn is then repeatedly generated during the same interval. When counting stops, set TCEn0 = 0. Figure 8-32. Timing of Interval Timer Operation (1/2) Basic operation t Count clock TMn count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N Count start CRn TCEn0 INTTMn N Interrupt acknowledgement TOn Interval time Interval time Interrupt acknowledgement Interval time Remark Interval time = (N + 1) x t; N = 0000H to FFFFH 228 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION Figure 8-32. Timing of Interval Timer Operation (2/2) When CRn = 0000H t Count clock TMn 0000H CRn TCEn0 INTTMn TOn 0000H 0000H 0000H 0000H Interval time When CRn = FFFFH t Count clock TMn CRn TCEn0 INTTMn Interrupt acknowledgement TOn Interval time Interrupt acknowledgement 0001H FFFFH FFFEH FFFFH 0000H FFFFH FFFEH FFFFH 0000H FFFFH User's Manual U14665EJ4V0UD 229 CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TIm. Each time a valid edge specified by timer clock selection register m0, m1 (TCLm0, TCLm1) is input, TMm is incremented. The edge setting can be selected to be either a rising or falling edge. If the total of TMm and the value of 16-bit compare register m (CRm) match, TMm is cleared to 0 and an interrupt request signal (INTTMm) is generated. INTTMm is generated each time the TMm value matches the CRm value. Figure 8-33. Timing of External Event Counter Operation (with Rising Edge specified) TIm TMm count value CRm INTTMm 0000H 0001H 0002H 0003H 0004H 0005H N-1 N N 0000H 0001H 0002H 0003H 230 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.3 Operation as square-wave output A square-wave with any frequency is output at the interval preset to 16-bit compare register m (CRm). By setting bit 0 (TOEm0) of 16-bit timer mode control register m0 (TMCm0) to 1, the output state of TOm is inverted at an interval specified by the count value preset to CRm. Therefore, a square-wave of any frequency (duty factor = 50%) can be output. Setting method (1) Set the registers. * Sets the port latch and port mode register to 0 * TCLm0, TCLm1: Selects the count clock * CRm: * TMCm0: Compare value Clear and start mode when TMm and CRm match LVSm0 1 0 LVRm0 0 1 Setting state of timer output flip-flop High-level output Low-level output Inversion of timer output flip-flop enabled Timer output enabled TOEm0 = 1 (2) When TCEm0 = 1 is set, the counter starts operating. (3) If the values of TMm and CRm match, the timer output flip-flop inverts. Also, INTTMm is generated and TMm is cleared to 0000H. (4) The timer output flip-flop is then inverted at the same interval and a square-wave is output from TOm. Figure 8-34. Square-Wave Output Operation Timing Count clock TMm count value 0000H 0001H 0002H Count start CRm TOm N N-1 N 0000H 0001H 0002H N-1 N 0000H Note The initial value of TOm output can be set using bits 3 and 2 (LVSm0, LVRm0) of the TMCm0 register. Remark Square-wave output frequency = Count clock frequency/2(N + 1) User's Manual U14665EJ4V0UD 231 CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.4 Operation as 16-bit PWM output By setting bit 6 (TMCm6) of 16-bit timer mode control register m0 (TMCm0) to 1, the timer operates as a PWM output. Pulses with the duty factor determined by the value set in 16-bit compare register m (CRm) are output from TOm. Set the width of the active level of the PWM pulse to CRm. The active level can be selected by bit 1 (TMCm01) of TMCm0. The count clock can be selected by bits 0 to 2 (TCLm0 to TCLm2) of timer clock selection register m0 (TCLm0) and by bit 0 (TCLm3) of timer clock selection register m1 (TCLm1). The PWM output can be enabled and disabled by bit 0 (TOEm0) of TMCm0. (1) Basic operation of the PWM output Setting method (1) Set the port latch and port mode register n to 0. (2) Set the active level width in 16-bit compare register m (CRm). (3) Select the count clock using timer clock selection register m0, m1 (TCLm0, TCLm1). (4) Set the active level in bit 1 (TMCm01) of TMCm0. (5) If bit 7 (TCEm0) of TMCm0 is set to 1, counting starts. To stop counting, set TCEm0 to 0. PWM output operation (1) When counting starts, the PWM output (output from TOm) outputs an inactive level until an overflow occurs. (2) When an overflow occurs, the active level specified in step (1) in the setting method is output. The active level is output until CRm and the count of 16-bit counter m (TMm) match. (3) The PWM output after CRm and the count match is the inactive level until an overflow occurs again. (4) Steps (2) and (3) repeat until counting stops. (5) If counting is stopped by TCEm0 = 0, PWM output goes to the inactive level. 232 User's Manual U14665EJ4V0UD CHAPTER 8 TIMER/COUNTER FUNCTION (a) Basic operation of PWM output Figure 8-35. Timing of PWM Output Basic operation (active level = H) Count clock TMm CRm TCEm0 INTTMm TOm 0000H 0001H N FFFFH 0000H 0001H 0002H N N+1 FFFFH 0000H 0001H 0002H M 0000H Active level Inactive level Active level When CRm = 0 Count clock TMm CRm TCEm0 INTTMm TOm 0000H 0001H 0000H FFFFH 0000H 0001H 0002H N N+1 N+2 FFFFH 0000H 0001H 0002H M 0000H Inactive level Inactive level When CRm = FFFFH Count clock TMm CRm TCEm0 INTTMm TOm Inactive level Active level 8 0000H 0001H FFFFH FFFFH 0000H 0001H 0002H N N+1 N+2 FFFFH 0000H 0001H 0002H M 0000H Inactive level Active level Inactive level Remark PWM output frequency = 2 t Duty = 256 (N: CRm register value) User's Manual U14665EJ4V0UD 233 CHAPTER 8 TIMER/COUNTER FUNCTION 8.4.5 Cautions (1) Error when the timer starts An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit counter n (TMn) is started asynchronously to the count pulse. Figure 8-36. Start Timing of Timer n Count pulse TMn count value 0000H Timer starts 0001H 0002H 0003H 0004H (2) TMn readout during timer operation Since reading out TMn during operation occurs while the selected clock is temporarily stopped, select a high- or low-level waveform that is longer than the selected clock. (3) Rewriting the compare register while 16-bit timers 2 to 6 (TM2 to TM6) are operating Stop the 16-bit timer count operation before changing the set value of 16-bit compare registers 2 to 6 (CR2 to CR6). 234 User's Manual U14665EJ4V0UD CHAPTER 9 WATCH TIMER FUNCTION 9.1 Function The watch timer has the following functions. * Watch timer * Interval timer The watch timer and interval timer functions can be used at the same time. Figure 9-1. Block Diagram of Watch Timer Clear Selector fXX fXT 11-bit prescaler fW 9 fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/2 Selector 5-bit counter Clear Selector INTWTN Selector INTWTNI 3 WTNCS1 WTNCS0 WTNM7 WTNM6 WTNM5 WTNM4 WTNM3 WTNM2 WTNM1 WTNM0 Watch timer clock selection register (WTNCS) Internal bus Watch timer mode control register (WTNM) Remark fXX: Main clock frequency fXT: Subclock frequency fW: Watch timer clock frequency User's Manual U14665EJ4V0UD 235 CHAPTER 9 WATCH TIMER FUNCTION (1) Watch timer The watch timer generates an interrupt request (INTWTN) at time intervals of 0.5 second or 0.25 second using the main clock or subclock. (2) Interval timer The watch timer generates an interrupt request (INTWTNI) at time intervals specified in advance. Table 9-1. Interval Time of Interval Timer Interval Time 2 x 1/fW 4 fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms 2 x 1/fW 5 2 x 1/fW 6 2 x 1/fW 7 2 x 1/fW 8 2 x 1/fW 9 2 x 1/fW 10 2 x 1/fW 11 Remark Watch timer clock frequency 9.2 Configuration The watch timer includes the following hardware. Table 9-2. Configuration of Watch Timer Item Counter Prescaler Control registers 5 bits x 1 11 bits x 1 Watch timer mode control register (WTNM) Watch timer clock selection register (WTNCS) Configuration 236 User's Manual U14665EJ4V0UD CHAPTER 9 WATCH TIMER FUNCTION 9.3 Watch Timer Control Register The watch timer mode control register (WTNM) and watch timer clock selection register (WTNCS) control the watch timer. The watch timer should be operated after setting the count clock. (1) Watch timer mode control register (WTNM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the interrupt time of the watch timer. WTNM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WTNM to 00H. After reset: 00H 7 WTNM WTNM7 R/W 6 WTNM6 Address: FFFFF360H 5 WTNM5 4 WTNM4 3 WTNM3 2 WTNM2 1 WTNM1 0 WTNM0 WTNM6 0 0 0 0 1 1 1 1 WTNM5 0 0 1 1 0 0 1 1 WTNM4 0 1 0 1 0 1 0 1 4 Selection of interval time of prescaler 2 /fW (488 s) 2 /fW (977 s) 5 2 /fW (1.95 ms) 2 /fW (3.91 ms) 2 /fW (7.81 ms) 2 /fW (15.6 ms) 2 /fW (31.2 ms) 2 /fW (62.4 ms) 11 10 9 8 7 6 WTNM3 0 0 1 1 WTNM2 0 1 0 1 2 /fW (0.5 s) 2 /fW (0.25 s) 2 /fW (977 s) 5 13 14 Selection of interrupt time of watch timer 2 /fW (488 s) 4 WTNM1 0 1 Operation of 5-bit counter Cleared after operation stops Operation starts WTNM0 0 1 Operation of watch timer Operation stopped (both prescaler and 5-bit counter cleared) Operation enabled Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply when fW = 32.768 kHz. 3. For the settings of WTNM7, refer to 9.3 (2) Watch timer clock selection register (WTNCS). User's Manual U14665EJ4V0UD 237 CHAPTER 9 WATCH TIMER FUNCTION (2) Watch timer clock selection register (WTNCS) This register selects the count clock of the watch timer. WTNCS is set by an 8-bit memory manipulation instruction. RESET input clears WTNCS to 00H. Caution Do not change the contents of the WTNM and WTNCS registers (interval time, watch timer interrupt time, count clock) during a watch timer operation. After reset: 00H 7 WTNCS 0 R/W 6 0 Address: FFFFF364H 5 0 4 0 3 0 2 0 1 WTNCS1 0 WTNCS0 WTNCS1 0 0 0 0 1 1 1 1 WTNCS0 0 0 1 1 0 0 1 1 WTNM7 0 1 0 1 0 1 0 1 Selection of count clock fXX/2 7 Main clock frequency 4.194 MHz - 6.291 MHz 8.388 MHz - - 12.582 MHz - fXT (subclock) fXX/3 x 2 fXX/2 8 6 Setting prohibited Setting prohibited fXX/3 x 2 7 Setting prohibited Remark WTNM7 is bit 7 of the WTNM register 238 User's Manual U14665EJ4V0UD CHAPTER 9 WATCH TIMER FUNCTION 9.4 Operation 9.4.1 Operation as watch timer The watch timer operates with time intervals of 0.5 second using the subclock (32.768 kHz). The watch timer generates an interrupt request at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTNM0) and 1 (WTNM1) of the watch timer mode control register (WTNM) are set to 1. When these bits are cleared to 0, the 11-bit prescaler and 5-bit counter are cleared, and the watch timer stops the count operation. The 5-bit counter of the watch timer can be cleared by setting the WTNM1 bit to 0, an error of up to 15.6 ms may occur at this time. Setting the WTNM0 bit to 0 can clear the interval timer. However, an error up to 0.5 sec. may occur after a watch timer overflow (INTWTN) because the 5-bit counter is also cleared. 9.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. The interval time can be selected by bits 4 to 6 (WTNM4 to WTNM6) of the watch timer mode control register (WTNM). Table 9-2. Interval Time of Interval Timer WTNM6 0 0 0 0 1 1 1 1 WTNM5 0 0 1 1 0 0 1 1 WTNM4 0 1 0 1 0 1 0 1 Interval Time 2 x 1/fW 4 fW = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.2 ms 62.4 ms 2 x 1/fW 5 2 x 1/fW 6 2 x 1/fW 7 2 x 1/fW 8 2 x 1/fW 9 2 x 1/fW 10 2 x 1/fW 11 Remark fW: Watch timer clock frequency User's Manual U14665EJ4V0UD 239 CHAPTER 9 WATCH TIMER FUNCTION Figure 9-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock fW or 9 fW/2 Watch timer interrupt INTWTN Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTNI Interval time (T) nT Interval time (T) nT Overflow Overflow Remark fW: Watch timer clock frequency The values in parentheses apply when the count clock is operating at fW = 32.768 kHz. n: Number of interval timer operations 9.4.3 Cautions It takes some time to generate the first watch timer interrupt request (INTWTN) after operation is enabled (WTNM1 and WTNM0 bits of WTNM register = 1). Figure 9-3. Watch Timer Interrupt Request (INTWTN) Generation (Interrupt Period = 0.5 s) It takes 0.515625 s to generate the first INTWTN (29 x 1/32.768 = 0.015625 s longer). INTWTN is then generated every 0.5 s. WTNM0, WTNM1 0.515625 s 0.5 s 0.5 s INTWTN 240 User's Manual U14665EJ4V0UD CHAPTER 10 WATCHDOG TIMER FUNCTION 10.1 Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer * Oscillation stabilization time selection Caution Use the watchdog timer mode register (WDTM) to select the watchdog timer mode or the interval timer mode. Figure 10-1. Block Diagram of Watchdog Timer RUN Clear fXX/212 Prescaler fXX/224 fXX/222 fXX/221 fXX/220 fXX/219 fXX/218 fXX/217 fXX/216 INTWDTNote 1 Output controller INTWDTMNote 2 Selector Selector OSC 3 3 WDCS WDCS2 WDCS1 WDCS0 OSTS OSTS2 OSTS1 OSTS0 WDTM RUN WDTM4 Internal bus Notes 1. 2. Remark In watchdog timer mode In interval timer mode fXX: Main clock frequency User's Manual U14665EJ4V0UD 241 CHAPTER 10 WATCHDOG TIMER FUNCTION (1) Watchdog timer mode This mode detects an inadvertent program loop. When a loop is detected, a non-maskable interrupt can be generated. Table 10-1. Loop Detection Time of Watchdog Timer Loop Detection Time fXX = 16 MHz 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 24 22 21 20 19 18 17 16 Clock 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 1.05 s fXX = 8 MHz 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 2.10 s (2) Interval timer mode Interrupts are generated at a preset time interval. Table 10-2. Interval Time of Interval Timer Interval Time fXX = 16 MHz 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 24 22 21 20 19 18 17 16 Clock 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 1.05 s fXX = 8 MHz 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 2.10 s 242 User's Manual U14665EJ4V0UD CHAPTER 10 WATCHDOG TIMER FUNCTION 10.2 Configuration The watchdog timer includes the following hardware. Table 10-3. Watchdog Timer Configuration Item Control registers Configuration Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) 10.3 Watchdog Timer Control Register The watchdog timer is controlled by the following registers. * Oscillation stabilization time selection register (OSTS) * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register (WDTM) (1) Oscillation stabilization time selection register (OSTS) This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable. OSTS is set by an 8-bit memory manipulation instruction. The value after RESET input differs depending on the device. 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y After reset: Note 7 OSTS 0 R/W 6 0 5 0 Address: FFFFF380H 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Oscillation stabilization time selection OSTS2 OSTS1 OSTS0 Clock 16 MHz 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx Setting prohibited 21 20 19 18 16 fxx 8 MHz 8.2 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 4.1 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms Other than above Note 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y User's Manual U14665EJ4V0UD 243 CHAPTER 10 WATCHDOG TIMER FUNCTION (2) Watchdog timer clock selection register (WDCS) This register selects the overflow times of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. After reset: 00H R/W Address: FFFFF382H 7 WDCS 0 6 0 5 0 4 0 3 0 2 WDCS2 1 WDCS1 0 WDCS0 Watchdog timer/interval timer overflow time WDCS2 WDCS1 WDCS0 Clock 16 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 24 22 21 20 19 18 17 16 fxx 8 MHz 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 2.10 s 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 1.05 s Caution Be sure to set bits 7 to 3 to 0. 244 User's Manual U14665EJ4V0UD CHAPTER 10 WATCHDOG TIMER FUNCTION (3) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables and disables counting. WDTM is set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets WDTM to 00H. After reset: 00H 7 WDTM RUN R/W 6 0 Address: FFFFF384H 5 0 4 WDTM4 3 0 2 0 1 0 0 0 RUN 0 1 Operation mode selection for the watchdog timer Count disabled Count cleared and counting starts Note 1 WDTM4 0 Operation mode selection for the watchdog timer Interval timer mode Note 2 (If an overflow occurs, a maskable interrupt, INTWDTM, is generated.) 1 Watchdog timer mode 1 (If an overflow occurs, a non-maskable interrupt, INTWDT, is generated.) Notes 1. 2. Caution Once RUN is set (1), the register cannot be cleared (0) by software. Therefore, when the count starts, the count cannot be stopped except by RESET input. Once WDTM4 is set (1), the register cannot be cleared (0) by software. If RUN is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 212/fXX seconds shorter than the set time. User's Manual U14665EJ4V0UD 245 CHAPTER 10 WATCHDOG TIMER FUNCTION 10.4 Operation 10.4.1 Operation as watchdog timer Set bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1 to operate as a watchdog timer to detect an inadvertent program loop. Setting bit 7 (RUN) of WDTM to 1 starts the count. After counting starts, if RUN is set to 1 again within the set time interval for loop detection, the watchdog timer is cleared and counting starts again. If RUN is not set to 1 and the loop detection time has elapsed, a non-maskable interrupt (INTWDT) is generated (no reset functions). The watchdog timer stops running in the IDLE mode and STOP mode. Consequently, set RUN to 1 and clear the watchdog timer before entering the IDLE mode or STOP mode. Note that overflow does not occur in the HALT mode since the watchdog timer continues running in HALT mode. Cautions 1. The actual loop detection time may be up to 212/fXX seconds shorter than the set time. 2. When the subclock is selected for the CPU clock, the watchdog timer stops counting (pauses). Table 10-4. Loop Detection Time of Watchdog Timer Loop Detection Time Clock fXX = 16 MHz 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 fxx 2 /fxx 24 22 21 20 19 18 17 16 fXX = 8 MHz 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 2.10 s 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 1.05 s 246 User's Manual U14665EJ4V0UD CHAPTER 10 WATCHDOG TIMER FUNCTION 10.4.2 Operation as interval timer Set bit 4 (WDTM4) to 0 in the watchdog timer mode register (WDTM) to operate the watchdog timer as an interval timer that repeatedly generates interrupts with a preset count value as the interval. When operating as an interval timer, the interrupt mask flag (WDTMK) of the WDTIC register and the priority setting flag (WDTPR0 to WDTPR2) become valid, and a maskable interrupt (INTWDTM) can be generated. The default priority of INTWDTM has the highest priority setting of the maskable interrupts. The interval timer continues operating in the HALT mode and stops in the IDLE mode and STOP mode. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (selecting the watchdog timer mode), the interval timer mode is not entered as long as RESET is not input. 2. The interval time immediately after being set by WDTM may be up to 212/fXX seconds shorter than the set time. 3. When the subclock is selected for the CPU clock, the watchdog timer stops counting (pauses). Table 10-5. Interval Time of Interval Timer Interval Time Clock fXX = 16 MHz 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx 24 22 21 20 19 18 17 16 fXX = 8 MHz 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 2.10 s 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 1.05 s User's Manual U14665EJ4V0UD 247 CHAPTER 10 WATCHDOG TIMER FUNCTION 10.5 Standby Function Control Register The wait time from when the stop mode is released until the oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. The value after RESET input differs depending on the device. 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y After reset: Note R/W Address: FFFFF380H 7 OSTS 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Oscillation stabilization time selection OSTS2 OSTS1 OSTS0 Clock 16 MHz 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 2 /fxx 2 /fxx 2 /fxx 2 /fxx 2 /fxx Setting prohibited 21 20 19 18 16 fXX 8 MHz 8.2 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 4.1 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms Other than above Note 01H: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 04H: PD703078Y, 703079Y, 70F3079Y Caution The wait time at the release of the STOP mode does not include the time ("a" in the figure below) until clock oscillation starts after STOP mode is released by RESET input or interrupt generation. STOP mode release Voltage waveform at X1 pin Vss a 248 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.1 Overview The V850/SF1 incorporates the following serial interfaces. * * * * Channel 0: 3-wire serial I/O (CSI0)/I2C0Note Channel 1: 3-wire serial I/O (CSI1)/Asynchronous serial interface (UART0) Channel 3: 3-wire serial I/O (CSI3)/Asynchronous serial interface (UART1) Channel 4: 8 to 16-bit variable-length 3-wire serial I/O (CSI4) Note I2C0 supports multiple masters. Either 3-wire serial I/O or I2C can be used as a serial interface. 11.2 3-Wire Serial I/O (CSI0, CSI1, CSI3) Remark n = 0, 1, 3 in section 11.2. CSIn has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. (2) 3-wire serial I/O mode (fixed to MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCKn), a serial output line (SOn), and a serial input line (SIn). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in the 8-bit data in serial transfers is fixed as the MSB. For the SCK0 pin, normal output or N-ch open-drain output can be selected by setting the port 1 function register (PF1). 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. User's Manual U14665EJ4V0UD 249 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.1 Configuration CSIn includes the following hardware. Table 11-1. Configuration of CSIn Item Registers Control registers Configuration Serial I/O shift register n (SIOn) Serial operation mode register n (CSIMn) Serial clock selection register n (CSISn) Figure 11-1. Block Diagram of 3-Wire Serial I/O Internal Bus 8 SIn Serial I/O shift register n (SIOn) SOn SCKn Serial clock counter Interrupt generator INTCSIn Serial clock controller Selector TMx output Clock selection Remark The following indicates the TMx output. When n = 0 or 3: TM2 When n = 1: TM3 (1) Serial I/O shift register n (SIOn) SIOn is an 8-bit register that performs parallel-serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. SIOn is set by an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIEn) of serial operation mode register n (CSIMn), a serial operation can be started by writing data to or reading data from SIOn. When transmitting, data written to SIOn is output via the serial output (SOn). When receiving, data is read from the serial input (SIn) and written to SIOn. RESET input clears these registers to 00H. Caution Do not access SIOn except via the transfer start trigger during a transfer operation (read is disabled when MODEn = 0 and write is disabled when MODEn = 1). 11.2.2 CSIn control registers CSIn is controlled by the following registers. * * Serial operation mode register n (CSIMn) Serial clock selection register n (CSISn) User's Manual U14665EJ4V0UD 250 CHAPTER 11 SERIAL INTERFACE FUNCTION (1) Serial operation mode register n (CSIMn) CSIMn is used to set the serial clock and operation modes, and enable or disable specific operations of serial interface channel n. CSIMn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H R/W Address: CSIM0 CSIM1 CSIM3 7 CSIMn CSIEn 6 0 5 0 4 0 FFFFF2A2H FFFFF2B2H FFFFF2D2H 3 0 2 MODEn 1 SCLn1 0 SCLn0 SIOn operation enable/disable specification CSIEn Shift register operation 0 1 Operation disabled Operation enabled Cleared Count operation enabled Serial counter Port function Port Note 1 Serial function + port function Note 2 Transfer operation mode flag MODEn Operation mode 0 1 Transmit/receive mode Receive-only mode Transfer start trigger SIOn write SIOn read SOn output Normal output Port function SCLn2 0 0 SCLn1 0 0 SCLn0 0 1 Clock selection External clock input (SCKn) at n = 0, 3: TM2 output at n = 1: TM3 output 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 fXX/8 fXX/16 Setting prohibited Setting prohibited fXX/32 fXX/64 Notes 1. 2. The SIn, SOn, and SCKn pins are used as port function pins when CSIEn = 0 (SIOn operation stop status). When CSIEn = 1 (SIOn operation enable status), the port function is available for the SIn pin when only using the transmit function and SOn pin when only using the receive function. Cautions 1. Do not perform bit manipulation of SCLn1 and SCLn0. 2. Be sure to set bits 6 to 3 of CSIMn to 0. Remarks 1. Refer to 11.2.2 (2) Serial clock selection register n (CSISn) for the SCLn2 bit. 2. When the selection clock is output as a timer, pins P30/TO2/TI2 and P31/TO3/TI3 do not need to be set in timer output mode. User's Manual U14665EJ4V0UD 251 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Serial clock selection register n (CSISn) CSISn is used to set the serial clock of serial interface channel n. CSISn can be set by an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. After reset : 00H R/W Address: CSIS0 CSIS1 CSIS3 7 CSISn 0 6 0 5 0 4 0 FFFFF2A4H FFFFF2B4H FFFFF2D4H 3 0 2 0 1 0 0 SCLn2 Remark Refer to 11.2.2 (1) Serial operation mode register n (CSIMn) for the setting of the SCLn2 bit. 11.2.3 Operations The CSIn has the following two operation modes. * * Operation stopped mode 3-wire serial I/O mode (1) Operation stopped mode In this mode, serial transfers are not performed and therefore power consumption can be reduced. When in operation stopped mode, SIn, SOn, and SCKn pins can be used as normal I/O port pins. (a) Register settings Operation stopped mode is set via the CSIEn bit of serial operation mode register n (CSIMn). Figure 11-2. CSIMn Setting (Operation Stopped Mode) After reset : 00H R/W Address: CSIM0 CSIM1 CSIM3 7 CSIMn CSIEn 6 0 5 0 4 0 FFFFF2A2H FFFFF2B2H FFFFF2D2H 3 0 2 MODEn 1 SCLn1 0 SCLn0 SIOn operation enable/disable specification CSIEn Shift register operation 0 Operation disabled Cleared Serial counter Port function Port 252 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (2) 3-wire serial I/O mode 3-wire serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCKn), a serial output line (SOn), and a serial input line (SIn). (a) Register settings 3-wire serial I/O mode is set by serial operation mode register n (CSIMn). Figure 11-3. CSIMn Setting (3-Wire Serial I/O Mode) After reset : 00H R/W Address: CSIM0 CSIM1 CSIM3 7 CSIMn CSIEn 6 0 5 0 4 0 FFFFF2A2H FFFFF2B2H FFFFF2D2H 3 0 2 MODEn 1 SCLn1 0 SCLn0 SIOn operation enable/disable specification CSIEn Shift register operation 1 Operation enabled Serial counter Count operation enabled Port Serial function + port function Transfer operation mode flag MODEn Operation mode 0 1 Transmit/receive mode Receive-only mode Transfer start trigger Write to SIOn Read from SIOn SOn output Normal output Port function SCLn2 0 0 SCLn1 0 0 SCLn0 0 1 Clock selection External clock input (SCKn) When n = 0, 3: TM2 output When n = 1: TM3 output 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 fXX/8 fXX/16 Setting prohibited Setting prohibited fXX/32 fXX/64 Remarks 1. Refer to 11.2.2 (1) Serial operation mode register n (CSIMn) and 11.2.2 (2) Serial clock selection register n (CSISn) for the SCLn2 bit. 2. When the selection clock is output as a timer, pins P30/TO2/TI2 and P31/TO3/TI3 do not need to be set in timer output mode. User's Manual U14665EJ4V0UD 253 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register n (SIOn) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SOn latch and is output from the SOn pin. Data that is received via the SIn pin in synchronization with the rising edge of the serial clock is latched to SIOn. Completion of an 8-bit transfer automatically stops operation of SIOn and sets the interrupt request flag (INTCSIn). Figure 11-4. Timing of 3-Wire Serial I/O Mode Serial clock SIn SOn INTCSIn 1 DI7 DO7 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0 Transfer completion Transfer starts in synchronization with the falling edge of the serial clock (c) Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I/O shift register n (SIOn). * The SIOn operation control bit (CSIEn) = 1 * After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. The transfer data to SIOn is set as follows. * Transmit/receive mode When CSIEn = 1 and MODEn = 0, transfer starts when writing to SIOn. * Receive-only mode When CSIEn = 1 and MODEn = 1, transfer starts when reading from SIOn. Caution After data has been written to SIOn, transfer will not start even if the CSIEn bit value is set to 1. Completion of an 8-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (INTCSIn). 254 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3 I2C Bus To use the I2C bus function, set the P10/SDA0 and P12/SCL0 pins to N-ch open drain output. I2C0 has the following two modes. * Operation stopped mode * I2C (Inter IC) bus mode (multiple masters supported) (1) Operation stopped mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multiple masters support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock line (SCL0) and a serial data bus line (SDA0). This mode complies with the I2C bus format and the master device can output "start condition", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received data by hardware. This function can simplify the part of an application program that controls the I2C bus. Since SCL0 and SDA0 are open-drain outputs, I2C0 requires pull-up resistors for the serial clock line and the serial data bus line. User's Manual U14665EJ4V0UD 255 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-5. Block Diagram of I2C0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) SDA0 Noise eliminator Slave address register 0 (SVA0) Match signal IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 CLEAR SET SO latch DQ CL01, CL00 IIC shift register 0 (IIC0) N-ch open drain output Data hold time correction circuit ACK detector Wakeup controller ACK detector Start condition detector SCL0 Noise eliminator Stop condition detector Interrupt request signal generator Serial clock counter INTIIC0 Serial clock controller N-ch open drain output fxx TM2 output Prescaler Serial clock wait controller CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC clock selection register 0 (IICCL0) CLX0 IICCE01 IICCE00 IIC clock expansion register 0 (IICCE0) IIC function expansion register 0 (IICX0) Internal bus 256 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 11-6. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 Slave CPU1 Address 1 SDA SCL Serial data bus Serial clock SDA SCL Master CPU2 Slave CPU2 Address 2 SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N User's Manual U14665EJ4V0UD 257 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.1 Configuration I2C0 includes the following hardware. Table 11-2. Configuration of I2C0 Item Registers Configuration IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC clock selection register 0 (IICCL0) IIC clock expansion register 0 (IICCE0) IICC function expansion register 0 (IICX0) (1) IIC shift register 0 (IIC0) IIC0 is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. IIC0 can be used for both transmission and reception. Write and read operations to IIC0 are used to control the actual transmit and receive operations. IIC0 is set by an 8-bit memory manipulation instruction. RESET input clears the IIC0 to 00H. (2) Slave address register 0 (SVA0) SVA0 sets local addresses when in slave mode. SVA0 is set by an 8-bit memory manipulation instruction. RESET input clears the SVA0 to 00H. (3) SO latch The SO latch is used to retain the SDA0 pin's output level. (4) Wakeup controller This circuit generates an interrupt request when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Clock selector This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. 258 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0). An I2C interrupt is generated following either of two triggers. * Eighth or ninth clock of the serial clock (set by WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by SPIE0 bit) Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0) SPIE0 bit: Bit 4 of IIC control register 0 (IICC0) (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK output circuit, stop condition detector, start condition detector, and ACK detector These circuits are used to output and detect various control signals. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. User's Manual U14665EJ4V0UD 259 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.2 I2C control registers I2C0 is controlled by the following registers. * IIC control register 0 (IICC0) * IIC status register 0 (IICS0) * IIC clock selection register 0 (IICCL0) * IIC clock expansion register 0 (IICCE0) * IIC function expansion register 0 (IICX0) The following registers are also used. * IIC shift register 0 (IIC0) * Slave address register 0 (SVA0) (1) IIC control register 0 (IICC0) IICC0 is used to enable/disable I2C operations, set wait timing, and set other I2C operations. IICC0 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets IICC0 to 00H. Caution In I2C0 bus mode, set the port 1 mode register (PM1) and port 1 function register (PF1) as follows. In addition, set each output latch to 0. Pin P10/SI0/SDA0 P12/SCK0/SCL0 Port Mode Register PM10 of PM1 register = 0 PM12 of PM1 register = 0 Port Function Register PF10 of PF1 register = 1 PF12 of PF1 register = 1 260 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (1/4) After reset: 00H 7 IICC0 IICE0 R/W 6 LREL0 5 WREL0 Address: FFFFF340H 4 SPIE0 3 WTIM0 2 ACKE0 1 STT0 0 SPT0 IICE0 0 1 I C0 operation enable/disable specification Operation stopped. IIC status register 0 (IICS0) preset. Internal operation stopped. Operation enabled. Condition for setting (IICE0 = 1) * Set by instruction 2 Condition for clearing (IICE0 = 0) * Cleared by instruction * When RESET is input LREL0 0 1 Normal operation Exit from communications This exits from the current communication operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0 and SDA0 lines are set to high impedance. The following flags are cleared. * STD0 * ACKD0 * TRC0 * COI0 * EXC0 * MSTS0 * STT0 * SPT0 The standby mode following exit from communications remains in effect until the following communication entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 = 0) * When RESET is input Note Condition for setting (LREL0 = 1) * Set by instruction * Automatically cleared after execution Note This flag's signal is invalid when IICE0 = 0. Remark STD0: ACKD0: TRC0: COI0: EXC0: MSTS0: Bit 1 of IIC status register 0 (IICS0) Bit 2 of IIC status register 0 (IICS0) Bit 3 of IIC status register 0 (IICS0) Bit 4 of IIC status register 0 (IICS0) Bit 5 of IIC status register 0 (IICS0) Bit 7 of IIC status register 0 (IICS0) User's Manual U14665EJ4V0UD 261 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/4) WREL0 0 1 Wait not canceled Wait cancellation control Wait canceled. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WREL0 = 0) * When RESET is input Condition for setting (WREL0 = 1) * Set by instruction * Automatically cleared after execution SPIE0 0 1 Disabled Enabled Enable/disable generation of interrupt request when stop condition is detected Condition for clearing (SPIE0 = 0) * Cleared by instruction * When RESET is input Note Condition for setting (SPIE0 = 1) * Set by instruction WTIM0 0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. This bit's setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 = 0) * Cleared by instruction * When RESET is input Note Condition for setting (WTIM0 = 1) * Set by instruction Note This flag's signal is invalid when IICE0 = 0. 262 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (3/4) ACKE0 0 1 Acknowledgement disable. Acknowledge control Acknowledgement enabled. During the ninth clock period, the SDA0 line is set to low level. However, ACK is invalid during address transfers and is valid when EXC0 = 1. Note Condition for clearing (ACKE0 = 0) * Cleared by instruction * When RESET is input Condition for setting (ACKE0 = 1) * Set by instruction STT0 0 1 Start condition not generated. When bus is released (in STOP mode): Start condition trigger Generates a start condition (for starting as master). The SDA0 line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL0 is changed to low level. When bus is not used: This trigger functions as a start condition reserve flag. When set, it releases the bus and then automatically generates a start condition. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set during transfer. Can be set only when ACKE0 has been set to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the ACK0 period. Set during the wait period. * Cannot be set at the same time as SPT0 Condition for clearing (STT0 = 0) * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When LREL0 = 1 * When IICE0 = 0 * Cleared when RESET is input Condition for setting (STT0 = 1) * Set by instruction Note This flag's signal is invalid when IICE0 = 0. Bit 1 (STT0) is 0 if it is read immediately after data setting. Remark User's Manual U14665EJ4V0UD 263 CHAPTER 11 SERIAL INTERFACE FUNCTION (4/4) SPT0 0 1 Stop condition is not generated. Stop condition trigger Stop condition is generated (termination of master device's transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line is changed from low level to high level and a stop condition is generated. Cautions concerning set timing * For master reception: Cannot be set during transfer. Can be set only when ACKE0 has been set to 0 and during the wait period after * For master transmission: slave has been notified of final reception. A stop condition cannot be generated normally during the ACK0 period. Set during the wait period. * Cannot be set at the same time as STT0. * SPT0 can be set only when in master mode Note . * When WTIM0 has been set to 0, if SPT0 is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. When a ninth clock must be output, WTIM0 should be changed from 0 to 1 during the wait period following output of eight clocks, and SPT0 should be set during the wait period that follows output of the ninth clock. Condition for clearing (SPT0 = 0) * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When LREL0 = 1 * When IICE0 = 0 * Cleared when RESET is input Condition for setting (SPT0 = 1) * Set by instruction Note Set SPT0 only in master mode. However, SPT0 must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. Cautions. Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance. Remark Bit 0 (SPT0) is 0 if it is read immediately after data setting. For details, see 11.3.13 264 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (2) IIC status register 0 (IICS0) IICS0 indicates the status of I2C0. IICS0 can be set by an 8-bit or 1-bit memory manipulation instruction. IICS0 is a read-only register. RESET input clears IICS0 to 00H. (1/3) After reset: 00H 7 IICS0 MSTS0 R 6 ALD0 5 EXC0 Address: FFFFF342H 4 COI0 3 TRC0 2 ACKD0 1 STD0 0 SPD0 MSTS0 0 1 Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTS0 = 1) * When a start condition is generated Condition for clearing (MSTS0 = 0) * When a stop condition is detected * When ALD0 = 1 * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 * When RESET is input ALD0 0 1 Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". MSTS0 is cleared. Condition for setting (ALD0 = 1) Note Condition for clearing (ALD0 = 0) * Automatically cleared after IICS0 is read * When IICE0 changes from 1 to 0 * When RESET is input * When the arbitration result is a "loss". EXC0 0 1 Extension code was not received. Extension code was received. Detection of extension code reception Condition for clearing (EXC0 = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 * When RESET is input Condition for setting (EXC0 = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICS0. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) User's Manual U14665EJ4V0UD 265 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/3) COI0 0 1 Addresses do not match. Addresses match. Condition for setting (COI0 = 1) * When the received address matches the local address (SVA0) (set at the rising edge of the eighth clock). Detection of matching addresses Condition for clearing (COI0 = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 * When RESET is input TRC0 0 1 Detection of transmit/receive status Receive status (other than transmit status). The SDA0 line is set to high impedance. Transmit status. The value in the SO latch is enabled for output to the SDA0 line (valid starting at the falling edge of the first byte's ninth clock). Condition for setting (TRC0 = 1) Master * When a start condition is generated Slave * When "1" is input by the first byte's LSB (transfer direction specification bit) Condition for clearing (TRC0 = 0) * When a stop condition is detected * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 Note * Cleared by WREL0 = 1 * When ALD0 changes from 0 to 1 * When RESET is input Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication Note TRC0 is cleared and the SDA0 line becomes high impedance when bit 5 (WREL0) of IIC control register 0 (IICC0) is set and the wait state is released at ninth clock by bit 3 (TRC0) of IIC status register 0 (IICS0) = 1. Remark WREL0: Bit 5 of IIC control register 0 (IICC0) LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) 266 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (3/3) ACKD0 0 1 ACK was not detected. ACK was detected. Detection of ACK Condition for clearing (ACKD0 = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 * When RESET is input Condition for setting (ACKD0 = 1) * After the SDA0 line is set to low level at the rising edge of the SCL0's ninth clock STD0 0 1 Start condition was not detected. Detection of start condition Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STD0 = 1) When a start condition is detected Condition for clearing (STD0 = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LREL0 = 1 * When IICE0 changes from 1 to 0 * When RESET is input SPD0 0 1 Stop condition was not detected. Detection of stop condition Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPD0 = 1) When a stop condition is detected Condition for clearing (SPD0 = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When IICE0 changes from 1 to 0 * When RESET is input Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) User's Manual U14665EJ4V0UD 267 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) IIC clock expansion register 0 (IICCE0), IIC function expansion register 0 (IICX0), IIC clock selection register 0 (IICCL0) These registers are used to set the transfer clock for I2C0. IICCE0 can be set by an 8-bit memory manipulation instruction, and IICX0 and IICCL0 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input sets these registers to 00H. (1/2) After reset: 00H 7 IICCE0 0 R/W 6 0 Address: FFFFF34CH 5 0 4 0 3 0 2 0 1 IICCE01 0 IICCE00 After reset: 00H 7 IICX0 0 R/W 6 0 Address: FFFFF34AH 5 0 4 0 3 0 2 0 1 0 <0> CLX0 After reset: 00H 7 IICCL0 0 R/W Note Address: FFFFF344H <5> CLD0 <4> DAD0 3 SMC0 2 DFC0 1 CL01 0 CL00 6 0 CLD0 0 1 Detection of SCL0 line level (valid only when IICE0 = 1) SCL0 line was detected at low level. SCL0 line was detected at high level. Condition for setting (CLD0 = 1) * When the SCL0 line is at high level Condition for clearing (CLD0 = 0) * When the SCL0 line is at low level * When IICE0 = 0 * When RESET is input DAD0 0 1 Detection of SDA0 line level (valid only when IICE0 = 1) SDA0 line was detected at low level. SDA0 line was detected at high level. Condition for setting (DAD0 = 1) * When the SDA0 line is at high level Condition for clearing (DAD0 = 0) * When the SDA0 line is at low level * When IICE0 = 0 * When RESET is input Note Bits 4 and 5 of IICCL0 are read-only bits. Caution Remark Be sure to set bits 7 and 6 of IICCL0 to 0. IICE0: Bit 7 of IIC control register 0 (IICC0) 268 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (2/2) SMC0 0 1 Operates in standard mode. Operates in high-speed mode. Operation mode switching DFC0 0 1 Digital filter off. Digital filter on. Digital filter operation control A digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFC0 switching (on/off). IICCE01 IICCE00 CLX0 SMC0 CL01 CL00 Selection clock (fXX/m) Settable main clock frequency (fXX) range Operation mode x x x 0 1 0 x x x 0 1 0 x x x 1 0 0 x x x 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 x x 0 1 1 1 0 1 0 1 1 1 fXX/12 fXX/24 fXX/48 fXX/36 fXX/54 TM2 output/18 4.0 MHz to 4.19 MHz 4.0 MHz to 8.38 MHz 8.0 MHz to 16.0 MHz 12.0 MHz to 13.4 MHz 16.0 MHz TM2 setting 4.0 MHz to 4.19 MHz 4.19 MHz to 8.38 MHz 8.38 MHz to 16.0 MHz 12.0 MHz to 13.4 MHz 16.0 MHz TM2 setting High-speed mode fXX/44 fXX/86 fXX/172 fXX/132 fXX/198 TM2 output/66 Normal mode Other than above Setting prohibited Remarks 1. x: don't care 2. If the selected clock is specified as the timer output, the P30/TO2/TI2 pin does not need to be in timer output mode. User's Manual U14665EJ4V0UD 269 CHAPTER 11 SERIAL INTERFACE FUNCTION (a) I2C0 transfer clock setting method The I2C0 transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 36, 54, 44, 86, 172, 132, 198 (see the descriptions for bits IICCE01, IICCE00, CLX0, SMC0, CL01, and CL00 in 11.3.2 (3).) T: tR: tF: 1/fXX SCL0 rise time SCL0 fall time For example, the I2C0 transfer clock frequency (fSCL) when fXX = 16 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using the following expression. fSCL = 1/(198 x 62.5 ns + 200 ns + 50 ns) 79.2 kHz Figure 11-7. I2C0 Transfer Clock Frequency (fSCL) m x T + tR + tF tR m/2 x T tF m/2 x T SCLn SCL0 inversion SCL0 inversion SCL0 inversion (4) IIC shift register 0 (IIC0) IIC0 is used for serial transmission/reception (shift operations) that are synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IIC0 during a data transfer. After reset: 00H 7 IIC0 R/W 6 Address: FFFFF348H 5 4 3 2 1 0 (5) Slave address register 0 (SVA0) SVA0 holds the I2C bus's slave addresses. It can be read from or written to in 8-bit units, but bit 0 should be fixed to 0. After reset: 00H 7 SVA0 R/W 6 Address: FFFFF346H 5 4 3 2 1 0 0 270 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.3 (1) I2C bus mode functions Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. SCL0 .............. This pin is used for serial clock I/O. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0 .............. This pin is used for serial data I/O. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 11-8. Pin Configuration Diagram VDD Slave device Master device SCL0 Clock output VDD (Clock input) SDA0 Data output SDA0 Data output Clock input SCL0 (Clock output) Data input Data input User's Manual U14665EJ4V0UD 271 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.4 I2C bus definitions and control methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. The transfer timing for the "start condition", "data", and "stop condition" output via the I2C bus's serial data bus is shown below. Figure 11-9. I2C Bus Serial Data Transfer Timing SCL0 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SDA0 Start Address condition R/W ACK Data ACK Data ACK Stop condition The master device outputs the start condition, slave address, and stop condition. The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCL0) is continuously output by the master device. However, in the slave device, SCL0's lowlevel period can be extended and a wait can be inserted. (1) Start condition A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The start conditions for the SCL0 pin and SDA0 pin are signals that the master device outputs to the slave device when starting a serial transfer. The slave device includes hardware for detecting start conditions. Figure 11-10. Start Conditions H SCL0 SDA0 A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 after a stop condition has been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of IICS0 is set to 1. 272 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit data matches the data values stored in slave address register 0 (SVA0). If the 7-bit data matches the SVA0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. Figure 11-11. Address SCL0 1 2 3 4 5 6 7 8 9 SDA0 AD6 AD5 AD4 AD3 Address AD2 AD1 AD0 R/W Note INTIIC0 Note INTIIC0 is generated if a local address or extension code is received during slave device operation. The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer direction specification below, are written together to IIC shift register 0 (IIC0) and are then output. Received addresses are written to IIC0. The slave address is assigned to the higher 7 bits of IIC0. User's Manual U14665EJ4V0UD 273 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 11-12. Transfer Direction Specification SCL0 1 2 3 4 5 6 7 8 9 SDA0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W Transfer direction specification Note INTIIC0 Note INTIIC0 is generated if a local address or extension code is received during slave device operation. 274 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device, it does not output an ACK signal after receiving the final data to be transmitted. The transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does not return an ACK signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an ACK signal may be caused by the following two factors. (a) Reception was not correctly performed. (b) The final data was received. When the receiving device sets the SDA0 line to low level during the ninth clock, the ACK signal becomes active (normal receive response). When bit 2 (ACKE0) of IIC control register 0 (IICC0) is set to 1, automatic ACK signal generation is enabled. Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRC0) of IIC status register 0 (IICS0) to be set. When this TRC0 bit's value is 0, it indicates receive mode. Therefore, ACKE0 should be set to 1. When the slave device is receiving (when TRC0 = 0), if the slave device does not need to receive any more data after receiving several bytes, setting ACKE0 to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRC0 = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting ACKE0 to 0 will prevent the ACK signal from being returned. This prevents the MSB data from being output via the SDA0 line (i.e., stops transmission) during transmission from the slave device. Figure 11-13. ACK Signal SCL0 1 2 3 4 5 6 7 8 9 SDA0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the eighth clock of SCL0 regardless of the ACKE0 value. No ACK signal is output if the received address is not a local address. The ACK signal output method during data reception is based on the wait timing setting, as described below. When 8-clock wait is selected: When 9-clock wait is selected: The ACK signal is output at the falling edge of the eighth clock of SCL0 if ACKE0 is set to 1 before wait cancellation. The ACK signal is automatically output at the falling edge of the eighth clock of SCL0 if ACKE0 has already been set to 1. User's Manual U14665EJ4V0UD 275 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. The slave device includes hardware that detects stop conditions. Figure 11-14. Stop Condition H SCL0 SDA0 A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4 (SPIE0) of IICC0 is set to 1. 276 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (6) Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin. Figure 11-15. Wait Signal (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (Master: transmission, slave: reception, and ACKE0 = 1) Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IIC0 data write (cancel wait) IIC0 SCL0 6 7 8 9 1 2 3 Slave Wait after output of eighth clock. FFH is written to IIC0 or WREL0 is set to 1. IIC0 SCL0 ACKE0 H Transfer lines SCL0 6 7 8 9 1 2 3 SDA0 D2 D1 D0 ACK D7 D6 D5 User's Manual U14665EJ4V0UD 277 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-15. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (Master: transmission, slave: reception, and ACKE0 = 1) Master IIC0 Master and slave both wait after output of ninth clock. IIC0 data write (cancel wait) SCL0 Slave IIC0 SCL0 6 7 8 9 1 2 3 FFH is written to IIC0 or WREL0 is set to 1. ACKE0 Transfer lines SCL0 H 6 7 8 9 1 2 3 SDA0 D2 D1 D0 ACK D7 D6 D5 Output according to previously set ACKE0 value Remark ACKE0: Bit 2 of IIC control register 0 (IICC0) WREL0: Bit 5 of IIC control register 0 (IICC0) A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0). Normally, when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written to IIC shift register 0 (IIC0), the wait status is canceled and the transmitting side writes data to IIC0 to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting bit 1 (STT0) of IICC0 to 1 * By setting bit 0 (SPT0) of IICC0 to 1 278 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.5 I2C interrupt request (INTIIC0) The following shows the value of IIC status register 0 (IICS0) at the INTIIC0 interrupt request generation timing and at the INTIIC0 interrupt timing. (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 RW AK 1 1: IICS0 = 10XXX110B 2: IICS0 = 10XXX000B 3: IICS0 = 10XXX000B (WTIM0 = 0) 4: IICS0 = 10XXXX00B 5: IICS0 = 00000001B D7 to D0 2 AK D7 to D0 3 AK 4 SP 5 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 RW AK 1 1: IICS0 = 10XXX110B 2: IICS0 = 10XXX100B 3: IICS0 = 10XXXX00B 4: IICS0 = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 279 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 5 SPT0 = 1 AK 6 SP 7 1: IICS0 = 10XXX110B 2: IICS0 = 10XXX000B (WTIM0 = 1) 3: IICS0 = 10XXXX00B (WTIM0 = 0) 4: IICS0 = 10XXX110B (WTIM0 = 0) 5: IICS0 = 10XXX000B (WTIM0 = 1) 6: IICS0 = 10XXXX00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 SPT0 = 1 AK 4 SP 5 1: IICS0 = 10XXX110B 2: IICS0 = 10XXXX00B 3: IICS0 = 10XXX110B 4: IICS0 = 10XXXX00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 280 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 RW AK 1 1: IICS0 = 1010X110B 2: IICS0 = 1010X000B 3: IICS0 = 1010X000B (WTIM0 = 1) 4: IICS0 = 1010XX00B 5: IICS0 = 00000001B D7 to D0 2 AK D7 to D0 3 AK 4 SP 5 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 RW AK 1 1: IICS0 = 1010X110B 2: IICS0 = 1010X100B 3: IICS0 = 1010XX00B 4: IICS0 = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 281 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (matches SVA0)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIM0 = 0 ST AD6 to AD0 RW AK 1 1: IICS0 = 0001X110B 2: IICS0 = 0001X000B 3: IICS0 = 0001X000B 4: IICS0 = 00000001B D7 to D0 2 AK D7 to D0 3 AK SP 4 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 ST AD6 to AD0 RW AK 1 1: IICS0 = 0001X110B 2: IICS0 = 0001X100B 3: IICS0 = 0001XX00B 4: IICS0 = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 282 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 4 AK SP 5 1: IICS0 = 0001X110B 2: IICS0 = 0001X000B 3: IICS0 = 0001X110B 4: IICS0 = 0001X000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 AK 4 SP 5 1: IICS0 = 0001X110B 2: IICS0 = 0001XX00B 3: IICS0 = 0001X110B 4: IICS0 = 0001XX00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 283 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW 3 AK D7 to D0 4 AK SP 5 1: IICS0 = 0001X110B 2: IICS0 = 0001X000B 3: IICS0 = 0010X010B 4: IICS0 = 0010X000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW 3 AK 4 D7 to D0 AK 5 SP 6 1: IICS0 = 0001X110B 2: IICS0 = 0001XX00B 3: IICS0 = 0010X010B 4: IICS0 = 0010X110B 5: IICS0 = 0010XX00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 284 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, mismatches address (= not extension code)) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICS0 = 0001X110B 2: IICS0 = 0001X000B 3: IICS0 = 00000X10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, mismatches address (= not extension code)) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICS0 = 0001X110B 2: IICS0 = 0001XX00B 3: IICS0 = 00000X10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 285 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIM0 = 0 ST AD6 to AD0 RW 1 1: IICS0 = 0010X010B 2: IICS0 = 0010X000B 3: IICS0 = 0010X000B 4: IICS0 = 00000001B AK D7 to D0 2 AK D7 to D0 3 AK SP 4 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 ST AD6 to AD0 RW 1 1: IICS0 = 0010X010B 2: IICS0 = 0010X110B 3: IICS0 = 0010X100B 4: IICS0 = 0010XX00B 5: IICS0 = 00000001B AK 2 D7 to D0 AK 3 D7 to D0 AK 4 SP 5 Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 286 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 4 AK SP 5 1: IICS0 = 0010X010B 2: IICS0 = 0010X000B 3: IICS0 = 0001X110B 4: IICS0 = 0001X000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 AK 5 SP 6 1: IICS0 = 0010X010B 2: IICS0 = 0010X110B 3: IICS0 = 0010XX00B 4: IICS0 = 0001X110B 5: IICS0 = 0001XX00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 287 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW 3 AK D7 to D0 4 AK SP 5 1: IICS0 = 0010X010B 2: IICS0 = 0010X000B 3: IICS0 = 0010X010B 4: IICS0 = 0010X000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW 4 AK 5 D7 to D0 AK 6 SP 7 1: IICS0 = 0010X010B 2: IICS0 = 0010X110B 3: IICS0 = 0010XX00B 4: IICS0 = 0010X010B 5: IICS0 = 0010X110B 6: IICS0 = 0010XX00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 288 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 = 0 (after restart, mismatches address (= not extension code)) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICS0 = 0010X010B 2: IICS0 = 0010X000B 3: IICS0 = 00000X10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 (after restart, mismatches address (= not extension code)) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 AK SP 5 1: IICS0 = 0010X010B 2: IICS0 = 0010X110B 3: IICS0 = 0010XX00B 4: IICS0 = 00000X10B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 289 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1> When WTIM0 = 0 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK D7 to D0 3 AK SP 4 1: IICS0 = 0101X110B (Example: when ALD0 is read during interrupt servicing) 2: IICS0 = 0001X000B 3: IICS0 = 0001X000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 SP 4 1: IICS0 = 0101X110B (Example: when ALD0 is read during interrupt servicing) 2: IICS0 = 0001X100B 3: IICS0 = 0001XX00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 290 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIM0 = 0 ST AD6 to AD0 RW 1 AK D7 to D0 2 AK D7 to D0 3 AK SP 4 1: IICS0 = 0110X010B (Example: when ALD0 is read during interrupt servicing) 2: IICS0 = 0010X000B 3: IICS0 = 0010X000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care <2> When WTIM0 = 1 ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 D7 to D0 AK 4 SP 5 1: IICS0 = 0110X010B (Example: when ALD0 is read during interrupt servicing) 2: IICS0 = 0010X110B 3: IICS0 = 0010X100B 4: IICS0 = 0010XX00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 291 CHAPTER 11 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 RW AK 1 D7 to D0 AK D7 to D0 AK SP 2 1: IICS0 = 01000110B (Example: when ALD0 is read during interrupt servicing) 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW 1 AK D7 to D0 AK D7 to D0 AK SP 2 1: IICSn = 0110X010B (Example: when ALD0 is read during interrupt servicing) IICC0's LREL0 is set to 1 via software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 292 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIM0 = 0 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK D7 to D0 AK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B (Example: when ALD0 is read during interrupt servicing) 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 <2> When WTIM0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B (Example: when ALD0 is read during interrupt servicing) 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 User's Manual U14665EJ4V0UD 293 CHAPTER 11 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches SVA0) ST AD6 to AD0 RW AK 1 D7 to Dn ST AD6 to AD0 RW AK 2 D7 to D0 AK SP 3 1: IICS0 = 1000X110B 2: IICS0 = 01000110B (Example: when ALD0 is read during interrupt servicing) 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care Dn = D6 to D0 <2> Extension code ST AD6 to AD0 RW AK 1 D7 to Dn ST AD6 to AD0 RW 2 AK D7 to D0 AK SP 3 1: IICS0 = 1000X110B 2: IICS0 = 0110X010B (Example: when ALD0 is read during interrupt servicing) IICC0's LREL0 is set to 1 via software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care Dn = D6 to D0 294 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 RW AK 1 D7 to Dn SP 2 1: IICS0 = 1000X110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care Dn = D6 to D0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 D7 to D0 AK SP 4 1: IICS0 = 1000X110B 2: IICS0 = 1000XX00B 3: IICS0 = 01000100B (Example: when ALD0 is read during interrupt servicing) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care User's Manual U14665EJ4V0UD 295 CHAPTER 11 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 SP 3 1: IICS0 = 1000X110B 2: IICS0 = 1000XX00B 3: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 D7 to D0 AK SP 4 1: IICS0 = 1000X110B 2: IICS0 = 1000XX00B 3: IICS0 = 01000000B (Example: when ALD0 is read during interrupt servicing) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 X: don't care 296 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.6 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) in IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown below. Table 11-3. INTIIC0 Generation Timing and Wait Control During Slave Device Operation WTIM0 Address 0 1 9 9 Notes 1, 2 Notes 1, 2 During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9 Data Reception 8 9 Note 2 Note 2 Data Transmission 8 9 Note 2 Note 2 Notes 1. The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (SVA0). At this point, ACK is output regardless of the value set to bit 2 (ACKE0) of IICC0. For a slave device that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock. 2. If the received address does not match the contents of slave address register 0 (SVA0), neither INTIIC0 nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) During address transmission/reception * Slave device operation: The interrupt and wait timing are determined regardless of the WTIM0 bit. of the WTIM0 bit. (2) During data reception * Master/slave device operation: The interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: The interrupt and wait timing are determined according to the WTIM0 bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 * By writing to the IIC shift register 0 (IIC0) * By start condition setting (bit 1 (STT0) of IIC control register 0 (IICC0) = 1) * By stop condition setting (bit 0 (SPT0) of IIC control register 0 (IICC0) = 1) When an 8-clock wait has been selected (WTIM0 = 0), the output level of ACK must be determined prior to wait cancellation. (5) Stop condition detection INTIIC0 is generated when a stop condition is detected. * Master device operation: The interrupt and wait timing occur at the falling edge of the ninth clock regardless User's Manual U14665EJ4V0UD 297 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.7 Address match detection method When in I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received. 11.3.8 Error detection In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0 (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. 11.3.9 Extension code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC0) is set for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected. (2) If 11110xx0 is set to SVA0 by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXC0 = 1 * Seven bits of data match: COI0 = 1 Note Note Note EXC0: Bit 5 of IIC status register 0 (IICS0) COI0: Bit 4 of IIC status register 0 (IICS0) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LREL0) of IIC control register 0 (IICC0) to 1 and the CPU will enter the next communication wait state. Table 11-4. Extension Code Bit Definitions Slave address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for different bus format 10-bit slave address specification Description 298 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.10 Arbitration When several master devices simultaneously output a start condition (when STT0 is set to 1 before STD0 is set to 1 Note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0) is set via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. For details of interrupt request timing, see 11.3.5 I2C interrupt request (INTIIC0). Note STD0: Bit 1 of IIC status register 0 (IICS0) STT0: Bit 1 of IIC control register 0 (IICC0) Figure 11-16. Arbitration Timing Example Master 1 SCL0 Hi-Z SDA0 Master 2 SCL0 Hi-Z Master 1 loses arbitration SDA0 Transfer lines SCL0 SDA0 User's Manual U14665EJ4V0UD 299 CHAPTER 11 SERIAL INTERFACE FUNCTION Table 11-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When data is at low level while attempting to output a restart condition When stop condition is detected while attempting to output a restart condition When data is at low level while attempting to output a stop condition When SCL0 is at low level while attempting to output a restart condition Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 When stop condition is output (when SPIE0 = 1) Note 2 Note 1 At falling edge of eighth or ninth clock following byte transfer Note 2 When stop condition is output (when SPIE0 = 1) At falling edge of eighth or ninth clock following byte transfer Note 1 Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM0 = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. Remark When there is a possibility that arbitration will occur, set SPIE0 = 1 for master device operation. SPIE0: Bit 5 of IIC control register 0 (IICC0) 11.3.11 Wakeup function The I2C bus slave function is a function that generates an interrupt request (INTIIC0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. However, when a stop condition is detected, bit 5 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. 300 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.12 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to "1"). If bit 1 (STT0) of IICC0 is set while the bus is not used, a start condition is automatically generated and the wait status is set after the bus is released (after a stop condition is detected). When the bus release is detected (when a stop condition is detected), writing to IIC shift register 0 (IIC0) causes the master's address transfer to start. At this point, bit 4 (SPIE0) of IICC0 should be set. When STT0 has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status. If the bus has been released.............................................. a start condition is generated If the bus has not been released (standby mode) .............. communication reservation To detect which operation mode has been determined for STT0, set STT0, wait for the wait period, then check the MSTS0 (bit 7 of IIC status register 0 (IICS0)). Wait periods, which should be set via software, are listed in Table 11-6. These wait periods can be set via the settings for bits 3, 1, and 0 (SMC0, CL01, and CL00) in IIC clock selection register 0 (IICCL0). Table 11-6. Wait Periods SMC0 0 0 0 0 1 1 1 1 CL01 0 0 1 1 0 0 1 1 CL00 0 1 0 1 0 1 0 1 Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks 32 clocks 13 clocks User's Manual U14665EJ4V0UD 301 CHAPTER 11 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 11-17. Communication Reservation Timing Program processing STT0 =1 Write to IIC0 Hardware processing Communication reservation Set SPD0 and INTIIC0 Set STD0 SCL0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 SDA0 Output by master with bus access IIC0: STT0: STD0: SPD0: IIC shift register 0 Bit 1 of IIC control register 0 (IICC0) Bit 1 of IIC status register 0 (IICS0) Bit 0 of IIC status register 0 (IICS0) Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0 (IICC0) to 1 before a stop condition is detected. Figure 11-18. Timing for Accepting Communication Reservations SCL0 SDA0 STD0 SPD0 Standby mode 302 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION The communication reservation flowchart is illustrated below. Figure 11-19. Communication Reservation Flowchart DI SET1 STT0 ; Sets STT0 flag (communication reservation). Define communication reservation ; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). Wait ; Secures wait period set by software (see Table 11-7). Note (Communication reservation) Yes MSTS0 = 0? ; Confirmation of communication reservation No (Generate start condition) Cancel communication reservation ; Clear user flag. IIC0 xxH ; IIC0 write operation EI Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop condition interrupt request occurs. User's Manual U14665EJ4V0UD 303 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. (a) Set IIC clock selection register 0 (IICCL0). (b) Set bit 7 (IICE0) of IIC control register 0 (IICC0). (c) Set bit 0 of IICC0. 304 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.14 Communication operations (1) Master operations The following is a flowchart of the master operations. Figure 11-20. Master Operation Flowchart START IICCL0 xxH Select transfer clock. IICC0 xxH IICE0 = SPIE0 = WTIM0= 1 INTIIC0 = 1? Yes Start IIC0 write transfer. No ; Stop condition detection INTIIC0 = 1? Yes ACKD0 = 1? Yes TRC0 = 1? Yes (transmit) Start IIC0 write transfer. No No Generate stop condition (no slave with matching address) No (receive) ; Address transfer completion WTIM0 = 0 ACKE0 = 1 WREL0 = 1 Start reception INTIIC0 = 1? No No INTIIC0 = 1? Data processing Yes Data processing ACKD0 = 1? No Yes Transfer completed? Yes ACKE0 = 0 No Generate restart condition or stop condition. User's Manual U14665EJ4V0UD 305 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Slave operation An example of slave operation is shown below. Figure 11-21. Slave Operation Flowchart START IICC0 xxH IICE0 = 1 INTIIC0 = 1? Yes EXC0 = 1? No No COI0 = 1? Yes TRC0 = 1? Yes WTIM0 = 1 Start IIC0 write transfer No Yes Communicate? Yes No LREL0 = 1 No WTIM0 = 0 ACKE0 = 1 WREL0 = 1 Start reception INTIIC0 = 1? Yes Data processing No INTIIC0 = 1? Yes Data processing ACKD0 = 1? No Yes Transfer completed? Yes Detect restart condition or stop condition ACKE0 = 0 No No 306 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.15 Timing of data communication When using I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction and then starts serial communication with the slave device. The shift operation of IIC bus shift register 0 (IIC0) is synchronized with the falling edge of the serial clock (SCL0). The transmit data is transferred to the SO latch and is output (MSB first) via the SDA0 pin. Data input via the SDA0 pin is captured by IIC0 at the rising edge of SCL0. The data communication timing is shown below. User's Manual U14665EJ4V0UD 307 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H IIC0 address IIC0 data Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When EXC0 = 1) TRC0 L Receive H H L L L Note IIC0 FFH Note Note To cancel slave wait, write FFH to IIC0 or set WREL0. 308 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H H L L L IIC0 data IIC0 data Transfer lines SCL0 SDA0 8 D0 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 1 D7 2 D6 3 D5 Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L Receive L L H H L L L Note Note IIC0 FFH Note IIC0 FFH Note Note To cancel master wait, write FFH to IIC0 or set WREL0. User's Manual U14665EJ4V0UD 309 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-22. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When SPIE0 = 1) TRC0 H Transmit L H H IIC0 data IIC0 address Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Stop condition IIC0 FFH Note 9 1 2 AD6 AD5 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 H H L L L Note IIC0 FFH Note Note (When SPIE0 = 1) TRC0 L Receive Note To cancel master wait, write FFH to IIC0 or set WREL0. 310 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-23. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 R 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note H H IIC0 address IIC0 FFH Note AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H L L L L IIC0 data Note To cancel master wait, write FFH to IIC0 or set WREL0. User's Manual U14665EJ4V0UD 311 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-23. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L Receive L L H H H L L Note Note IIC0 FFH Note IIC0 FFH Note Transfer lines SCL0 SDA0 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5 Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H L L L L IIC0 data IIC0 data Note To cancel master wait, write FFH to IIC0 or set WREL0. 312 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-23. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When SPIE0 = 1) TRC0 Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 N- ACK Stop condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When SPIE0 = 1) TRC0 H H L L L IIC0 data 1 2 Note H H IIC0 FFH Note IIC0 address AD6 AD5 Start condition Note To cancel master wait, write FFH to IIC0 or set WREL0. User's Manual U14665EJ4V0UD 313 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4 Asynchronous Serial Interface (UART0, UART1) Remark n = 0, 1 in section 11.4. UARTn has the following two operation modes. (1) Operation stopped mode This mode is used when serial transfers are not performed. consumption. (2) Asynchronous serial interface mode This mode enables full-duplex operation in which one byte of data is transmitted and received after the start bit. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates. In addition, a baud rate based on divided clock input to the ASCKn pin can also be defined. The UARTn baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). 11.4.1 Configuration UARTn includes the following hardware. Table 11-7. Configuration of UARTn Item Registers Configuration Transmit shift registers 0, 1 (TXS0, TXS1) Receive buffer registers 0, 1 (RXB0, RXB1) Control registers Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) Baud rate generator mode control registers 00, 01 (BRGMC00, BRGMC01) Baud rate generator mode control registers 10, 11 (BRGMC10, BRGMC11) It can therefore be used to reduce power 314 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-24. Block Diagram of UARTn Internal Bus 8 Receive buffer registers 0, 1 (RXB0, RXB1) 8 RXD0, RXD1 TXD0, TXD1 Receive shift registers 0, 1 (RX0, RX1) 8 Transmit shift registers 0, 1 (TXS0, TXS1) Receive control parity check Baud rate generator INTSR0, INTSR1 Transmit control parity addition INTST0, INTST1 Selector fXX to fXX/2 TMx output 9 ASCK0, ASCK1 Remark The following indicates the TMx output. When UART0: TM2 When UART1: TM3 (1) Transmit shift registers 0, 1 (TXS0, TXS1) TXSn is the register for setting transmit data. Data written to TXSn is transmitted as serial data. When the data length is set as 7 bits, bit 0 to bit 6 of the data written to TXSn is transmitted as serial data. Writing data to TXSn starts the transmit operation. TXSn can be written to by an 8-bit memory manipulation instruction. It cannot be read. RESET input sets these registers to FFH. Caution Do not write to TXSn during a transmit operation. (2) Receive shift registers 0, 1 (RX0, RX1) RXn register converts serial data input via the RXD0, RXD1 pins to parallel data. When one byte of data is received at RXn, the received data is transferred to receive buffer registers 0 and 1 (RXB0, RXB1). RX0 and RX1 cannot be manipulated directly by a program. (3) Receive buffer registers 0, 1 (RXB0, RXB1) RXBn is used to hold receive data. transferred. When the data length is set as 7 bits, received data is sent to bit 0 to bit 6 of RXBn. In RXBn, the MSB must be set to "0". RXBn can be read by an 8-bit memory manipulation instruction. It cannot be written. RESET input sets RXBn to FFH. When one byte of data is received, one byte of new receive data is User's Manual U14665EJ4V0UD 315 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Transmission controller The transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register n (TXSn), based on the values set to asynchronous serial interface mode register n (ASIMn). (5) Reception controller The reception controller controls receive operations based on the values set to asynchronous serial interface mode register n (ASIMn). During a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register n (ASISn) according to the type of error that is detected. 11.4.2 UARTn control registers UARTn is controlled by the following registers. * * * * Asynchronous serial interface mode register n (ASIMn) Asynchronous serial interface status register n (ASISn) Baud rate generator control register n (BRGCn) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) 316 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) ASIMn is an 8-bit register that controls UARTn's serial transfer operations. ASIMn can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H 7 R/W 6 RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 UCLn 2 SLn 1 ISRMn 0 0 ASIMn TXEn TXEn 0 0 1 1 RXEn 0 1 0 1 Operation mode Operation stopped UARTn mode (receive only) UARTn mode (transmit only) UARTn mode (transmit and receive) RXDn/Pxx pin function Port function Serial function Port function Serial function TXDn/Pxx pin function Port function Port function Serial function Serial function PS1n 0 0 PS0n 0 1 No parity Parity bit specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) 1 1 0 1 Odd parity Even parity UCLn 0 1 7 bits 8 bits Character length specification SLn 0 1 1 bit 2 bits Stop bit length specification for transmit data ISRMn 0 1 Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has been stopped. 2. Be sure to set bit 0 to 0. User's Manual U14665EJ4V0UD 317 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error. ASISn can be read by an 8-bit or 1-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H 7 ASISn 0 R 6 0 Address: FFFFF302H, FFFFF312H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn PEn 0 1 No parity error Parity error (Transmit data parity does not match) Parity error flag FEn 0 1 No framing error Framing error Note 1 Framing error flag (Stop bit not detected) OVEn 0 1 No overrun error Overrun error Note 2 Overrun error flag (Next receive operation was completed before data was read from receive buffer register) Notes 1. Even if a stop bit length has been set as two bits by setting bit 2 (SLn) in asynchronous serial interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has occurred. Until the contents of RXBn are read, further overrun errors will occur when receiving data. 318 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Baud rate generator control registers 0, 1 (BRGC0, BRGC1) These registers set the serial clock for UARTn. BRGCn can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H 7 BRGCn MDLn7 R/W 6 MDLn6 Address: FFFFF304H, FFFFF314H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0 MD Ln7 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln6 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln5 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln4 0 0 0 0 0 0 0 0 0 1 * * * 1 MD Ln3 0 1 1 1 1 1 1 1 1 0 * * * 1 MD Ln2 x 0 0 0 0 1 1 1 1 0 * * * 1 MD Ln1 x 0 0 1 1 0 0 1 1 0 * * * 1 MD Ln0 x 0 1 0 1 0 1 0 1 0 * * * 1 fSCK/255 Selection of input clock Setting prohibited fSCK/8 fSCK/9 fSCK/10 fSCK/11 fSCK/12 fSCK/13 fSCK/14 fSCK/15 fSCK/16 * * * k - 8 9 10 11 12 13 14 15 16 * * * 255 Cautions 1. The value of BRGCn becomes 00H after reset. Before starting operation, select a setting other than "Setting prohibited". Selecting the "Setting prohibited" setting in stop mode does not cause any problems. 2. If write is performed to BRGCn during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. Therefore, do not write to BRGCn during communication processing. Remark fSCK: Source clock of 8-bit counter User's Manual U14665EJ4V0UD 319 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) These registers set the UARTn source clock. BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. After reset: 00H 7 BRGMCn0 0 R/W 6 0 Address: FFFFF30EH, FFFFF31EH 5 0 4 0 3 0 2 TPSn2 1 TPSn1 0 TPSn0 After reset: 00H 7 BRGMCn1 0 R/W 6 0 Address: FFFFF320H, FFFFF322H 5 0 4 0 3 0 2 0 1 0 0 TPSn3 TPSn3 0 0 0 0 0 0 0 0 TPSn2 0 0 0 0 1 1 1 1 TPSn1 0 0 1 1 0 0 1 1 TPSn0 0 1 0 1 0 1 0 1 8-bit counter source clock selection External clock (ASCKn) fxx fxx/2 fxx/4 fxx/8 fxx/16 fxx/32 at n = 0: TM2 output at n = 1: TM3 output m - 0 1 2 3 4 5 - 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/64 fxx/128 fxx/256 fxx/512 Setting prohibited 6 7 8 9 - - - - Cautions. 1. If write is performed to BRGMCn0, n1 during communication processing, the output of the baud rate generator will be disturbed and communication will not be performed normally. Therefore, do not write to BRGMCn0, n1 during communication processing. 2. Be sure to set bits 7 to 3 of BRGMCn0 to 0. Remarks 1. fSCK: Source clock of 8-bit counter 2. When the selection clock is output from the timer, pins P30/TO2/TI2 and P31/TO3/TI3 do not need to be set to timer output mode. 320 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.3 Operations UARTn has the following two operation modes. * * Operation stopped mode Asynchronous serial interface mode (1) Operation stopped mode In this mode, serial transfers are not performed and therefore power consumption can be reduced. When in operation stopped mode, pins can be used as ordinary ports. (a) Register settings Operation stopped mode settings are made via bits TXEn and RXEn of asynchronous serial interface mode register n (ASIMn). Figure 11-25. ASIMn Setting (Operation Stopped Mode) After reset: 00H 7 ASIMn TXEn R/W 6 RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 CLn 2 SLn 1 ISRMn 0 0 TXEn 0 RXEn 0 Operation mode Operation stopped RXDn/Pxx pin function Port function TXDn/Pxx pin function Port function Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has been stopped. 2. Be sure to set bit 0 to 0. User's Manual U14665EJ4V0UD 321 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode This mode enables full-duplex operation in which one byte of data after the start bit is transmitted and received. The on-chip dedicated UARTn baud rate generator enables communications using a wide range of selectable baud rates. The UARTn baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). (a) Register settings The asynchronous serial interface mode settings are made via ASIMn, BRGCn, BRGMCn0, and BRGMCn1. Figure 11-26. ASIMn Setting (Asynchronous Serial Interface Mode) After reset: 00H 7 ASIMn TXEn R/W 6 RXEn Address: FFFFF300H, FFFFF310H 5 PS1n 4 PS0n 3 CLn 2 SLn 1 ISRMn 0 0 TXEn 0 1 1 RXEn 1 0 1 Operation mode UARTn mode (receive only) UARTn mode (transmit only) UARTn mode (transmit and receive) RXDn/Pxx pin function Serial function Port function Serial function TXDn/Pxx pin function Port function Serial function Serial function PS1n 0 0 1 1 PS0n 0 1 0 1 No parity Parity bit specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity CLn 0 1 7 bits 8 bits Character length specification SLn 0 1 1 bit 2 bits Stop bit length specification for transmit data ISRMn 0 1 Receive completion interrupt control when error occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has been stopped. 2. Be sure to set bit 0 to 0. 3. Set the RXEn to 1 after a high level is input to the RXDn pin. If the RXEn is set to 1 when the RXDn pin is at low level, reception is started unexpectedly. 322 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-27. ASISn Setting (Asynchronous Serial Interface Mode) After reset: 00H 7 ASISn 0 R 6 0 Address: FFFFF302H, FFFFF312H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn PEn 0 1 No parity error Parity error (Transmit data parity does not match) Parity error flag FEn 0 1 No framing error Framing error Note 1 Framing error flag (Stop bit not detected) OVEn 0 1 No overrun error Overrun error Note 2 Overrun error flag (Next receive operation was completed before data was read from receive buffer register) Notes 1. Even if the stop bit length has been set as two bits by setting bit 2 (SLn) of asynchronous serial interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has occurred. Until the contents of RXBn are read, further overrun errors will occur when receiving data. User's Manual U14665EJ4V0UD 323 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-28. BRGCn Setting (Asynchronous Serial Interface Mode) After reset: 00H 7 BRGCn MDLn7 R/W 6 MDLn6 Address: FFFFF304H, FFFFF314H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0 MD Ln7 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln6 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln5 0 0 0 0 0 0 0 0 0 0 * * * 1 MD Ln4 0 0 0 0 0 0 0 0 0 1 * * * 1 MD Ln3 0 1 1 1 1 1 1 1 1 0 * * * 1 MD Ln2 x 0 0 0 0 1 1 1 1 0 * * * 1 MD Ln1 x 0 0 1 1 0 0 1 1 0 * * * 1 MD Ln0 x 0 1 0 1 0 1 0 1 0 * * * 1 fSCK/255 Input clock selection Setting prohibited fSCK/8 fSCK/9 fSCK/10 fSCK/11 fSCK/12 fSCK/13 fSCK/14 fSCK/15 fSCK/16 * * * k - 8 9 10 11 12 13 14 15 16 * * * 255 Cautions 1. Reset input clears BRGCn to 00H. Before starting operation, select a setting other than "Setting prohibited". Selecting "Setting prohibited" setting in stop mode does not cause any problems. 2. If write is performed to BRGCn during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. Therefore, do not write to BRGCn during communication processing. Remark fSCK: Source clock of 8-bit counter 324 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-29. BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) After reset: 00H 7 BRGMCn0 0 R/W 6 0 Address: FFFFF30EH, FFFFF31EH 5 0 4 0 3 0 2 TPSn2 1 TPSn1 0 TPSn0 After reset: 00H 7 BRGMCn1 0 R/W 6 0 Address: FFFFF320H, FFFFF322H 5 0 4 0 3 0 2 0 1 0 0 TPSn3 TPSn3 0 0 0 0 0 0 0 0 TPSn2 0 0 0 0 1 1 1 1 TPSn1 0 0 1 1 0 0 1 1 TPSn0 0 1 0 1 0 1 0 1 8-bit counter source clock selection External clock (ASCKn) fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 at n = 0: TM3 output at n = 1: TM2 output m - 0 1 2 3 4 5 - 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/64 fXX/128 fXX/256 fXX/512 Setting prohibited 6 7 8 9 - - - - Cautions 1. If write is performed to BRGMCn0, n1 during communication processing, the output of the baud rate generator is disturbed and communication will not be performed normally. Therefore, do not write to BRGMCn0 and BRGMCn1 during communication processing. 2. Be sure to set bits 7 to 3 of BRGMCn0 to 0. Remarks 1. fXX: Main clock oscillation frequency 2. When the selection clock is output from the timer, pins P30/TO2/TI2 and P31/TO3/TI3 do not need to be set in timer output mode. User's Manual U14665EJ4V0UD 325 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Baud rate The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. * Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock. fxx: Main clock oscillation frequency m: Value set by TPSn3 to TPSn0 (0 m 9) k: Value set by MDLn7 to MDLn0 (8 k 255) * Baud rate error tolerance The baud rate error tolerance depends on the number of bits in a frame and the counter division ratio [1/(16+k)]. Table 11-8 shows the relationship between the main clock and the baud rate, and Figure 11-30 shows an example of the baud rate error tolerance. Table 11-8. Relationship Between Main Clock and Baud Rate Baud Rate (bps) 32 64 128 300 600 1200 2400 4800 9600 19200 38400 76800 150000 300000 k - 244 244 208 208 208 208 208 208 208 208 104 53 27 fXX = 16 MHz m - 9 8 7 6 5 4 3 2 1 0 0 0 0 Error (%) - 0.06 0.06 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.63 -1.24 k 244 244 244 208 208 208 208 208 208 208 104 52 27 13 fXX = 8 MHz m 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Error (%) 0.06 0.06 0.06 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.24 2.56 Remark fXX: Main clock oscillation frequency 326 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-30. Error Tolerance (When k = 16), Including Sampling Errors Ideal sampling point 32T 64T 256T 288T 320T 352T 304T Basic timing (clock cycle T) High-speed clock (clock cycle T') enabling normal reception Low-speed clock (clock cycle T") enabling normal reception START D0 D7 P 15.5T 336T STOP START 30.45T START D0 60.9T D0 33.55T 67.1T D7 P STOP 304.5T 15.5T Sampling error 0.5T STOP D7 301.95T P 335.5T Remark T: 8-bit counter's source clock cycle 15.5 320 Baud rate error tolerance (when k = 16) = x 100 = 4.8438 (%) User's Manual U14665EJ4V0UD 327 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Communication operations (a) Data format As shown in Figure 11-31, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. Asynchronous serial interface mode register n (ASIMn) is used to set the character bit length, parity selection, and stop bit length within each data frame. Figure 11-31. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start bit Parity bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 * Start bit ............. 1 bit * Character bits ... * Parity bit ........... * Stop bit(s) ........ 7 bits or 8 bits Even parity, odd parity, zero parity, or no parity 1 bit or 2 bits When 7 bits is selected as the number of character bits, only the lower 7 bits (from bit 0 to bit 6) are valid, so during a transmission the most significant bit (bit 7) is ignored and during reception the most significant bit (bit 7) must be set to 0. Asynchronous serial interface mode register n (ASIMn) and baud rate generator control register n (BRGCn) are used to set the serial transfer rate. If a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register n (ASISn). 328 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the oddnumber bit) can be detected. When zero parity or no parity is set, errors are not detected. (i) Even parity * During transmission The number of bits in transmit data including a parity bit is controlled so that an even number of "1" bits is set. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: The parity bit value is "1" If the transmit data contains an even number of "1" bits: The parity bit value is "0" * During reception The number of "1" bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an odd number. (ii) Odd parity * During transmission The number of bits in transmit data including a parity bit is controlled so that an odd number of "1" bits is set. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits: The parity bit value is "0" If the transmit data contains an even number of "1" bits: The parity bit value is "1" * During reception The number of "1" bits is counted among the receive data including a parity bit, and a parity error is generated when the result is an even number. (iii) Zero parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, the parity bit is not checked. Therefore, no parity errors will be generated regardless of whether the parity bit is a "0" or a "1". (iv) No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will be generated. User's Manual U14665EJ4V0UD 329 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Transmission A transmit operation is started when transmit data is written to transmit shift register n (TXSn). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting a transmit operation shifts out the data in TXSn, thereby emptying TXSn, after which a transmit completion interrupt (INTSTn) is issued. The timing of the transmit completion interrupt is shown below. Figure 11-32. Timing of Asynchronous Serial Interface Transmit Completion Interrupt (a) Stop bit length: 1 TxDn (output) START D0 D1 D2 D6 D7 Parity STOP INTSTn (b) Stop bit length: 2 TxDn (output) START D0 D1 D2 D6 D7 Parity STOP INTSTn Caution Do not write to asynchronous serial interface mode register n (ASIMn) during a transmit operation. Writing to ASIMn during a transmit operation may disable further transmit operations (in such cases, enter a RESET to restore normal operation). Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (INTSTn) or the interrupt request flag (STIFn) that is set by INTSTn. 330 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (d) Reception A receive operation is enabled when bit 6 (RXEn) of asynchronous serial interface mode register n (ASIMn) is set to 1, and input via the RXDn pin is sampled. The serial clock specified by BRGCn is used when sampling the RXDn pin. When the RXDn pin goes low, the 8-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the RXDn pin input with this start timing signal yields a low-level result, the start bit is recognized, after which the 8-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. Once reception of one data frame is complete, the receive data in the shift register is transferred to receive buffer register n (RXBn) and a receive completion interrupt (INTSRn) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXBn. When an error occurs, INSTRn is generated if bit 1 (ISRMn) of ASIMn is cleared (0). On the other hand, INTSRn is not generated if the ISRMn bit is set (1). If the RXEn bit is reset to 0 during a receive operation, the receive operation is stopped immediately. At this time, the contents of RXBn and ASISn do not change, nor does INTSRn or INTSERn occur. The timing of the asynchronous serial interface receive completion interrupt is shown below. Figure 11-33. Timing of Asynchronous Serial Interface Receive Completion Interrupt RXDn (input) START D0 D1 D2 D6 D7 Parity STOP INTSRn Caution Be sure to read the contents of receive buffer register n (RXBn) even when a receive error has occurred. If the contents of RXBn are not read, an overrun error will occur during the next data receive operation and the receive error status will remain. User's Manual U14665EJ4V0UD 331 CHAPTER 11 SERIAL INTERFACE FUNCTION (e) Receive error There are three types of errors during a receive operation: a parity error, a framing error, and an overrun error. When, as the result of data reception, an error flag is set in asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated. The receive error interrupt request is generated prior to the receive completion interrupt request (INTSRn). By reading the contents of ASISn during receive error interrupt servicing (INTSERn), it is possible to detect which error has occurred at reception. The contents of ASISn are reset (0) by reading receive buffer register n (RXBn) or receiving subsequent data (if there is an error in the subsequent data, the error flag is set). Table 11-9. Receive Error Causes Receive Error Parity error Framing error Overrun error Cause Parity specification at transmission and receive data parity do not match. Stop bit is not detected. Reception of subsequent data was completed before data was read from the receive buffer register. ASISn Value 04H 02H 01H Figure 11-34. Receive Error Timing RxDn (Input) START D0 D1 D2 D6 D7 Parity STOP INTSRnNote INTSERn INTSERn (When parity error occurs) Note Even if a receive error occurs when the ISRMn bit of ASIMn is set (1), INTSRn is not generated. Cautions 1. The contents of asynchronous serial interface status register n (ASISn) are reset (0) by reading receive buffer register n (RXBn) or receiving subsequent data. To check the contents of an error, be sure to read ASISn before reading RXBn. 2. Be sure to read receive buffer register n (RXBn) even when a receive error has been generated. If RXBn is not read out, an overrun error will occur during subsequent data reception and as a result receive errors will continue to occur. 332 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.4.4 Standby function (1) Operation in HALT mode Serial transfer operations are performed normally. (2) Operation in STOP and IDLE modes (a) When internal clock is selected as serial clock The operations of asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), and receive buffer register n (RXBn) are stopped and their values immediately before the clock stopped are held. The TXDn pin output holds the data immediately before the clock is stopped (in STOP mode) during transmission. When the clock is stopped during reception, the receive data until the clock stopped is stored and subsequent receive operations are stopped. Reception resumes upon clock restart. (b) When external clock is selected as serial clock Serial transfer operations are performed normally. User's Manual U14665EJ4V0UD 333 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5 3-Wire Variable-Length Serial I/O (CSI4) CSI4 has the following two operation modes. (1) Operation stopped mode This mode is used when serial transfers are not performed. (2) 3-wire variable-length serial I/O mode (MSB/LSB first switchable) This mode transfers variable data of 8 to 16 bits via three lines: a serial clock line (SCK4), a serial output line (SO4), and a serial input line (SI4). Since data can be transmitted and received simultaneously in 3-wire variable-length serial I/O mode, the processing time of data transfer is shortened. MSB and LSB can be switched for the first bit of data to be transferred in serial. 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. 11.5.1 Configuration CSI4 includes the following hardware. Table 11-10. Configuration of CSI4 Item Register Control registers Configuration Variable-length serial IO shift register 4 (SIO4) Variable-length serial control register 4 (CSIM4) Variable-length serial setting register 4 (CSIB4) Baud rate generator source clock selection register 4 (BRGCN4) Baud rate generator output clock selection register 4 (BRGCK4) 334 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-35. Block Diagram of 3-Wire Variable-Length Serial I/O Internal bus Direction controller SI4 Variable length I/O shift register 4 (8/16 bits) SO4 Serial clock counter (8-/16-bit switchable) Interrupt generator INTCSI4 SCK4 Serial clock controller Selector Baud rate generator (1) Variable-length serial I/O shift register 4 (SIO4) SIO4 is a 16-bit variable register that performs parallel-serial conversion and transmission/reception (shift operations) in synchronization with the serial clock. SIO4 is set by a 16-bit memory manipulation instruction. A serial operation starts when data is written to or read from SIO4, while bit 7 (CSIE4) of variable-length serial control register 4 (CSIM4) is 1. When transmitting, data written to SIO4 is output via the serial output (SO4). When receiving, data is read from the serial input (SI4) and written to SIO4. RESET input clears SIO4 to 0000H. Caution Do not access SIO4 except via the transfer start trigger during a transfer operation (read is disabled when MODE4 = 0 and write is disabled when MODE4 = 1). After reset: 0000H R/W Address: FFFFF2E0H 15 SIO4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 User's Manual U14665EJ4V0UD 335 CHAPTER 11 SERIAL INTERFACE FUNCTION When the transfer bit length is set to other than 16 bits and data is set to the shift register, data should be aligned from the lowest bit of the shift register, regardless of whether MSB or LSB is set for the first transfer bit. Any data can be set to the unused higher bits, however, in this case the data received after a serial transfer operation becomes 0. Figure 11-36. When Transfer Bit Length Other Than 16 Bits Is Set (a) When transfer bit length is 10 bits and MSB first SO4 15 10 9 0 SI4 Fixed to 0 (b) When transfer bit length is 12 bits and LSB first SI4 15 12 11 0 SO4 Fixed to 0 336 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.2 CSI4 control registers CSI4 is controlled by the following registers. * * * * Variable-length serial control register 4 (CSIM4) Variable-length serial setting register 4 (CSIB4) Baud rate generator source clock selection register 4 (BRGCN4) Baud rate generator output clock selection register 4 (BRGCK4) (1) Variable-length serial control register 4 (CSIM4) This register is used to enable or disable the serial clock, operation modes, and specific operations of serial interface channel 4. CSIM4 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CSIM4 to 00H. After reset: 00H 7 CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4 SIO4 operation enable/disable specification CSIE4 Shift register operation 0 1 Operation disabled Operation enabled Cleared Count operation enabled Serial counter Port function Port Note 1 Serial function + port function Note 2 Transfer operation mode flag MODE4 Operation mode 0 1 Transmit/receive mode Receive-only mode Transfer start trigger SIO4 write SIO4 read SO4 output Normal output Port function SCL4 0 1 External clock input (SCK4) BRG (Baud rate generator) Clock selection Notes 1. 2. When CSIE4 = 0 (SIO4 operation disabled status), the port function is available for the SI4, SO4, and SCK4 pins. When CSIE4 = 1 (SIO4 operation enabled status), the port function is available for the SI4 pin when using the transmit function only and for the SO4 pin when using the dedicated receive function. User's Manual U14665EJ4V0UD 337 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Variable-length serial setting register 4 (CSIB4) CSIB4 is used to set the operation format of serial interface channel 4. The bit length of a variable register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. CSIB4 can be set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CSIB4 to 00H. After reset : 00H 7 CSIB4 0 R/W 6 CMODE Address: FFFFF2E4H 5 DMODE 4 DIR 3 BSEL3 2 BSEL2 1 BSEL1 0 BSEL0 CMODE 0 0 1 1 DMODE 0 1 0 1 SCK4 active level Low level Low level High level High level SI4 interrupt timing Rising edge of SCK4 Falling edge of SCK4 Falling edge of SCK4 Rising edge of SCK4 SO4 output timing Falling edge of SCK4 Rising edge of SCK4 Rising edge of SCK4 Falling edge of SCK4 DIR 0 1 LSB first MSB first Serial transfer direction BSEL3 0 1 1 1 1 1 1 1 1 BSEL2 0 0 0 0 0 1 1 1 1 BSEL1 0 0 0 1 1 0 0 1 1 BSEL0 0 0 1 0 1 0 1 0 1 16 bits 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits Bit length of serial register Other than above Setting prohibited 338 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Baud rate generator source clock selection register 4 (BRGCN4) BRGCN4 can be set by an 8-bit memory manipulation instruction. RESET input clears BRGCN4 to 00H. After reset : 00H 7 BRGCN4 0 R/W 6 0 Address: FFFFF2E6H 5 0 4 0 3 0 2 BRGN2 1 BRGN1 0 BRGN0 BRGN2 0 0 0 0 1 1 1 1 BRGN1 0 0 1 1 0 0 1 1 BRGN0 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Source clock (fSCK) m 0 1 2 3 4 5 6 7 User's Manual U14665EJ4V0UD 339 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Baud rate generator output clock selection register 4 (BRGCK4) BRGCK4 is set by an 8-bit memory manipulation instruction. RESET input sets BRGCK4 to 7FH. After reset : 7FH 7 BRGCK4 0 R/W 6 BRGK6 Address: FFFFF2E8H 5 BRGK5 4 BRGK4 3 BRGK3 2 BRGK2 1 BRGK1 0 BRGK0 BRGK6 0 0 0 0 * * * BRGK5 0 0 0 0 * * * BRGK4 0 0 0 0 * * * BRGK3 0 0 0 0 * * * BRGK2 0 0 0 0 * * * BRGK1 0 0 1 1 * * * BRGK0 0 1 0 1 * * * Baud rate output clock Setting prohibited fSCK/2 fSCK/4 fSCK/6 * * * k 0 1 2 3 * * * 1 1 1 1 1 1 1 1 1 1 1 1 0 1 fSCK/252 fSCK/254 126 127 The baud rate transmit/receive clock that is generated is obtained by dividing the main clock. * Generation of baud rate transmit/receive clock using main clock The transmit/receive clock is obtained by dividing the main clock. The following equation is used to obtain the baud rate from the main clock. fXX: Main clock oscillation frequency m: Value set by BRGN2 to BRGN0 (0 m 7) k: Caution Value set by BRGK6 to BRGK0 (1 k 127) Do not use the baud rate transmit/receive clock of the variable-length serial I/O (CSI4) with a transfer rate higher than the CPU operation clock. If used with a transfer rate higher than the CPU operation clock, transfer cannot be performed correctly. 340 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION 11.5.3 Operations CSI4 has the following two operation modes. * Operation stopped mode * 3-wire variable-length serial I/O mode (1) Operation stopped mode In this mode, serial transfers are not performed, and therefore power consumption can be reduced. When in operation stopped mode, SI4, SO4, and SCK4 can be used as normal I/O ports. (a) Register settings Operation stopped mode is set via the CSIE4 bit of variable-length serial control register 4 (CSIM4). While CSIE4 = 0 (SIO4 operation stopped state), the pins connected to SI4, SO4, or SCK4 function as port pins. Figure 11-37. CSIM4 Setting (Operation Stopped Mode) After reset : 00H 7 CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4 SIO4 operation enable/disable specification CSIE4 Shift register operation 0 Operation disabled Cleared Serial counter Port function Port User's Manual U14665EJ4V0UD 341 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) 3-wire variable-length serial I/O mode 3-wire variable-length serial I/O mode is useful when connecting to a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK4), a serial output line (SO4), and a serial input line (SI4). (a) Register settings 3-wire variable-length serial I/O mode is set using variable-length serial control register 4 (CSIM4). Figure 11-38. CSIM4 Setting (3-Wire Variable-Length Serial I/O Mode) After reset : 00H 7 CSIM4 CSIE4 R/W 6 0 Address: FFFFF2E2H 5 0 4 0 3 0 2 MODE4 1 0 0 SCL4 SIO4 operation enable/disable specification CSIE4 Shift register operation 1 Operation enabled Serial counter Count operation enabled Port Serial function + port function Transfer operation mode flag MODE4 Operation mode 0 Transmit-only or transmit/receive mode 1 Receive-only mode Read from SIO4 Port function Transfer start trigger Write to SIO4 SO4 output Normal output SCL4 0 1 External clock input (SCK4) BRG (Baud rate generator) Serial clock selection 342 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION The bit length of a variable-length register is set by setting bits 3 to 0 (BSEL3 to BSEL0) of CSIB4. Data is transferred MSB first while bit 4 (DIR) is 1, and is transferred LSB first while DIR is 0. Figure 11-39. CSIB4 Setting (3-Wire Variable-Length Serial I/O Mode) After reset : 00H 7 CSIB4 0 R/W 6 CMODE Address: FFFFF2E4H 5 DMODE 4 DIR 3 BSEL3 2 BSEL2 1 BSEL1 0 BSEL0 CMODE 0 0 1 1 DMODE 0 1 0 1 SCK4 active level Low level Low level High level High level SI4 interrupt timing Rising edge of SCK4 Falling edge of SCK4 Falling edge of SCK4 Rising edge of SCK4 SO4 output timing Falling edge of SCK4 Rising edge of SCK4 Rising edge of SCK4 Falling edge of SCK4 DIR 0 1 LSB first MSB first Serial transfer direction BSEL3 0 1 1 1 1 1 1 1 1 BSEL2 0 0 0 0 0 1 1 1 1 BSEL1 0 0 0 1 1 0 0 1 1 BSEL0 0 0 1 0 1 0 1 0 1 16 bits 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits Bit length of serial register Other than above Setting prohibited User's Manual U14665EJ4V0UD 343 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Communication operations In 3-wire variable-length serial I/O mode, data is transmitted and received in 8- to 16-bit units, and is specified by setting bits 3 to 0 (BSEL3 to BSEL0) of variable-length serial setting register 4 (CSIB4). Each bit of data is transmitted or received in synchronization with the serial clock. After transfer of all bits is complete, SIO4 stops operation automatically and the interrupt request flag (INTCSI4) is set. Bits 6 and 5 (CMODE and DMODE) of variable-length serial setting register 4 (CSIB4) can change the attribute of the serial clock (SCK4) and the phases of serial data (SI4 and SO4). Figure 11-40. Timing of 3-Wire Variable-Length Serial I/O Mode SCK4 (CMODE = 0) SCK4 (CMODE = 1) SIO4 (Write) SO4 (DMODE = 0) SO4 (DMODE = 1) INTCSI4 Remark The arrow shows the SI4 data fetch timing. When CMODE = 0, the serial clock (SCK4) stops at a high level while the operation is stopped, and outputs a low level during a data transfer operation. When CMODE = 1, on the other hand, SCK4 stops at a low level while the operation is stopped and outputs a high level during a data transfer operation. The phases of the SO4 output timing and the S14 fetch timing can be shifted half a clock by setting DMODE. However, the interrupt signal (INTCSI4) is generated at the final edge of the serial clock (SCK4), regardless of the setting of CSIB4. 344 User's Manual U14665EJ4V0UD CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Transfer start A serial transfer becomes possible when the following two conditions have been satisfied. * The SIO4 operation control bit (CSIE4) = 1 * After a serial transfer, the internal serial clock is stopped. Serial transfer starts when the following operation is performed after the above two conditions have been satisfied. * Transmit/transmit and receive mode (MODE4 = 0) Transfer starts when writing to SIO4. * Receive-only mode (MODE4 = 1) Transfer starts when reading from SIO4. Caution After data has been written to SIO4, transfer will not start even if the CSIE4 bit is set to 1. Completion of the final-bit transfer automatically stops the serial transfer operation and sets the interrupt request flag (INTCSI4). Figure 11-41. Timing of 3-Wire Variable-Length Serial I/O Mode (When CSIB4 = 08H) SCK4 (CMODE = 0) SO4 (DMODE = 0) SI4 INTCSI4 Transfer end 1 LSB 2 3 4 5 6 7 8 MSB LSB MSB Remark CSIB4 = 08H (CMODE = 0, DMODE = 0, DIR = 0, BSEL3 to BSEL0 = 1000) User's Manual U14665EJ4V0UD 345 CHAPTER 12 A/D CONVERTER 12.1 Function The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The V850/SF1 supports low-speed conversion and a low-power consumption mode. (1) Hardware start Conversion is started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified). (2) Software start Conversion is started by setting A/D converter mode register 1 (ADM1). One analog input channel is selected from ANI0 to ANI11, and A/D conversion is performed. If A/D conversion has been started by means of a hardware start, conversion stops once it has been completed, and an interrupt request (INTAD) is generated. If conversion has been started by means of a software start, conversion is performed repeatedly. Each time conversion has been completed, INTAD is generated. 346 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER The block diagram is shown below. Figure 12-1. Block Diagram of A/D Converter ADCVDD ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 Sample & hold circuit Voltage comparator ADCGND Successive approximation register (SAR) Tap selector Selector ADCGND ADTRG Edge detector Controller INTAD 4 Trigger enable ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 A/D conversion result register (ADCR) EGA1 EGA0 ADPS IEAD A/D converter mode register 2 (ADM2) Analog input channel specification register (ADS) A/D converter mode register 1 (ADM1) Internal bus User's Manual U14665EJ4V0UD 347 CHAPTER 12 A/D CONVERTER 12.2 Configuration The A/D converter includes the following hardware units. Table 12-1. Configuration of A/D Converter Item Analog input Registers Configuration 12 channels (ANI0 to ANI11) Successive approximation register (SAR) A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Control registers A/D converter mode register 1 (ADM1) A/D converter mode register 2 (ADM2) Analog input channel specification register (ADS) (1) Successive approximation register (SAR) This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the result of the comparison starting from the most significant bit (MSB). When the comparison result has been obtained down to the least significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Each time A/D conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register. The higher 10 bits of this register hold the result of the A/D conversion (the lower 6 bits are fixed to 0). This register is read by a 16-bit memory manipulation instruction. RESET input sets ADCR to 0000H. When using only the higher 8 bits of the result of the A/D conversion, ADCRH is read by an 8-bit memory manipulation instruction. RESET input sets ADCRH to 00H. Caution A write operation to A/D converter mode register 1 (ADM1) and the analog input channel specification register (ADS) may cause the ADCR contents to be undefined. Therefore, read the A/D conversion result during an A/D conversion operation (ADCS = 1). conversion results may not be read if the timing is other than the above. (3) Sample & hold circuit The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) Series resistor string The series resistor string is connected between ADCVDD and ADCGND and generates a voltage for comparison with the analog input signal. Correct 348 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (6) ANI0 to ANI11 pins These are analog input pins for the 12 channels of the A/D converter, and are used to input the analog signals to be converted into digital signals. Pins other than ones selected for analog input using the analog input channel specification register (ADS) can be used as input ports. Caution Make sure that the voltages input to ANI0 through ANI11 do not exceed the rated values. If a voltage higher than or equal to ADCVDD or lower than or equal to ADCGND (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel becomes undefined, and the conversion values of the other channels may also be affected. (7) ADCGND pin This is the ground pin of the A/D converter. Always make the potential at this pin the same as that at the GND0 pin even when the A/D converter is not in use. (8) ADCVDD pin This is the analog power supply pin of the A/D converter. Always make the potential at this pin the same as that at the VDD0 pin even when the A/D converter is not in use. User's Manual U14665EJ4V0UD 349 CHAPTER 12 A/D CONVERTER 12.3 Control Registers The A/D converter is controlled by the following registers. * * * A/D converter mode register 1 (ADM1) Analog input channel specification register (ADS) A/D converter mode register 2 (ADM2) (1) A/D converter mode register 1 (ADM1) This register specifies the conversion time of the input analog signal to be converted into a digital signal, starting or stopping the conversion, and an external trigger. ADM1 is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears ADM1 to 00H. 350 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (1/2) After reset: 00H 7 ADM1 ADCS ADCS 0 1 TRG 0 1 Software start Hardware start Selection of conversion time ADPS FR2 FR1 FR0 Conversion time Note 2 + stabilization time 168/fXX 120/fXX 84/fXX 60/fXX 48/fXX 36/fXX Setting prohibited 12/fXX 168/fXX + 84/fXX 120/fXX + 60/fXX 84/fXX + 42/fXX 60/fXX + 30/fXX 48/fXX + 24/fXX 36/fXX + 18/fXX Setting prohibited 12/fXX + 6/fXX Note 1 R/W 6 TRG Address: FFFFF3C0H 5 FR2 4 FR1 3 FR0 A/D conversion control 2 EGA1 1 EGA0 0 ADPS Conversion stopped Conversion enabled Software start or hardware start selection Sampling time 16 MHz 28/fXX 20/fXX 14/fXX 10/fXX 8/fXX 6/fXX Setting prohibited 2/fXX 28/fXX 20/fXX 14/fXX 10/fXX 8/fXX 6/fXX Setting prohibited 2/fXX Setting prohibited 7.5 s 5.25 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 7.5 + 3.75 s 5.25 + 2.625 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited fXX 8 MHz Setting prohibited Setting prohibited Setting prohibited 7.5 s 6.0 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 7.5 + 3.75 s 6.0 + 3.0 s Setting prohibited Setting prohibited Setting prohibited 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1. Conversion time (actual A/D conversion time). Be sure to set the time to 5 s Conversion time 10 s. The sampling time is included. Moreover, it takes the INTAD occurrence delay time (= 4/fXX) until INTAD occurrence. 2. Stabilization time (setup time of A/D converter) Each A/D conversion requires "conversion time + stabilization time". There is no stabilization time when ADPS = 0. User's Manual U14665EJ4V0UD 351 CHAPTER 12 A/D CONVERTER (2/2) EGA1 0 0 1 1 EGA0 0 1 0 1 Valid edge specification for external trigger signal No edge detection Detection at falling edge Detection at rising edge Detection at both rising and falling edges ADPS 0 1 Comparator on Comparator off Comparator control while A/D conversion is stopped (ADCS = 0) Cautions 1. The time from conversion trigger input to sampling start differs depending on the ADPS bit value. The conversion time is the same. If the ADPS bit is cleared (0) immediately before conversion, it is necessary to wait for the comparator stabilization time before setting the start trigger. 2. The A/D converter cannot be used when the operation frequency is 3.6 MHz or lower. 3. Cut the current consumption by setting the ADPS bit to 1 when the ADCS bit is set to 0. 352 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS) ADS specifies the port for inputting the analog voltage to be converted into a digital signal. ADS is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears ADS to 00H. After reset: 00H 7 ADS 0 R/W 6 0 Address: FFFFF3C2H 5 0 4 0 3 ADS3 2 ADS2 1 ADS1 0 ADS0 ADS3 0 0 0 0 0 0 0 0 1 1 1 1 ADS2 0 0 0 0 1 1 1 1 0 0 0 0 ADS1 0 0 1 1 0 0 1 1 0 0 1 1 ADS0 0 1 0 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 Analog input channel specification Other than above Setting prohibited Caution Be sure to set bits 7 to 4 to 0. (3) A/D converter mode register 2 (ADM2) ADM2 specifies connection/disconnection of ADCVDD and the series resistor string. ADM2 is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears ADM2 to 00H. After reset: 00H 7 ADM2 0 R/W 6 0 Address: FFFFF3C8H 5 0 4 0 3 0 2 0 1 0 0 IEAD IEAD 0 1 A/D current cut control Cut between ADCVDD and series resistor string Connect between ADCVDD and series resistor string User's Manual U14665EJ4V0UD 353 CHAPTER 12 A/D CONVERTER 12.4 Operation 12.4.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal by using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3> After sampling for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until it has been converted into a digital signal. <4> Set bit 9 of the successive approximation register (SAR). The tap selector sets the voltage tap of the series resistor string to (1/2) ADCVDD. <5> The voltage difference between the voltage tap of the series resistor string and the analog input voltage is compared by the voltage comparator. If the analog input voltage is greater than (1/2) ADCVDD, the MSB of the SAR remains set. If the analog input voltage is less than (1/2) ADCVDD, the MSB is reset. <6> Next, bit 8 of the SAR is automatically set, and the analog input voltage is compared again. Depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows: * * Bit 9 = 1: (3/4) ADCVDD Bit 9 = 0: (1/4) ADCVDD The analog input voltage is compared with one of these voltage taps, and bit 8 of the SAR is manipulated as follows depending on the result of the comparison. * Analog input voltage voltage tap: Bit 8 = 1 * Analog input voltage voltage tap: Bit 8 = 0 <7> The above steps are repeated until bit 0 of the SAR has been manipulated. <8> When comparison of all 10 bits of the SAR has been completed, the valid digital value remains in the SAR, and the value of the SAR is transferred and latched to the A/D conversion result register (ADCR). At the same time, an A/D conversion end interrupt request (INTAD) can be generated. Caution The first conversion value immediately after setting ADCS = 0 1 may not satisfy the ratings. 354 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER Figure 12-2. Basic Operation of A/D Converter Conversion time Sampling time Operation of A/D converter Sampling A/D conversion SAR Undefined Conversion result ADCR Conversion result INTAD A/D conversion is successively executed until bit 7 (ADCS) of A/D converter mode register 1 (ADM1) is reset to 0 by software. If ADM1 and the analog input channel specification register (ADS) are written during A/D conversion, the conversion is initialized. If ADCS is set to 1 at this time, conversion is started from the beginning. RESET input clears the A/D conversion result register (ADCR) to 0000H. User's Manual U14665EJ4V0UD 355 CHAPTER 12 A/D CONVERTER Figure 12-3. A/D Conversion by Software Start/Hardware Start (When ADPS Bit = 0) When ADPS = 0, software start ADCS Input (E) A/D conversion (B) A/D conversion (E) Wait Processing format Sampling Wait Sampling INTAD (B) (C) When ADPS = 0, hardware start Trigger edge Input (G) Input (A) (D) (C) (D) Processing format Sampling A/D conversion Standby status Sampling A/D conversion INTAD (F) (A) (B) (C) (D) (F) (A) (B) A: A/D conversion start delay time (= 4/fXX) B: Sampling time (see 12.3 (1) A/D converter mode register 1 (ADM1)) C: Conversion time (see 12.3 (1) A/D converter mode register 1 (ADM1)) D: INTAD occurrence delay time (= 4/fXX) E: Wait time during successive conversion (= 7/fXX) F: Valid edge detection time (= 2/fXX to 3/fXX) G: External trigger input cycle (= C + H + 8/fXX to 9/fXX) 356 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER Figure 12-4. A/D Conversion by Software Start/Hardware Start (When ADPS Bit = 1) When ADPS = 1, software start ADCS Input (E) A/D conversion Wait (H) (B) Processing format Stabilization time Sampling Stabilization time Sampling A/D conversion INTAD (B) (C) When ADPS = 0, hardware start Trigger edge Input Standby status Input (A) (H) (D) Processing format Stabilization time Sampling A/D conversion Stabilization time Sampling INTAD (F) (A) (H) (B) (C) (D) (F) (A) (H) (B) A: A/D conversion start delay time (= 4/fXX) B: Sampling time (see 12.3 (1) A/D converter mode register 1 (ADM1)) C: Conversion time (see 12.3 (1) A/D converter mode register 1 (ADM1)) D: INTAD occurrence delay time (= 4/fXX) E: F: G: H: Wait time during successive conversion (= 7/fXX) Valid edge detection time (= 2/fXX to 3/fXX) External trigger input cycle (= C + H + 8/fXX to 9/fXX) Stabilization time (see 12.3 (1) A/D converter mode register 1 (ADM1)) User's Manual U14665EJ4V0UD 357 CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion result The analog voltages input to the analog input pins (ANI0 to ANI11) and the result of the A/D conversion (contents of the A/D conversion result register (ADCR)) are related as follows: ADCR = INT( Or, (ADCR - 0.5) x INT ( ): VIN: ADCR: ADCVDD 1024 VIN < (ADCR + 0.5) x ADCVDD 1024 VIN x 1024 + 0.5) ADCVDD Function that returns integer of value enclosed in parentheses Analog input voltage Value of the A/D conversion result register (ADCR) ADCVDD: A/D converter reference voltage The relationship between the analog input voltage and A/D conversion result is shown below. Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1023 1022 A/D conversion result (ADCR) 1021 3 2 1 0 1 1 3 2 5 3 2048 1024 20481024 2048 1024 2043 1022 20451023 2047 1 2048 1024 20481024 2048 Input voltage/ADCVDD 358 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode In this mode one of the analog input channels ANI0 to ANI11 is selected by the analog input channel specification register (ADS) and A/D conversion is executed. A/D conversion can be started in the following two ways. * Hardware start: Software start: Started by trigger input (ADTRG) (rising edge, falling edge, or both rising and falling edges can be specified) Started by setting A/D converter mode register 1 (ADM1) * The result of the A/D conversion is stored in the A/D conversion result register (ADCR) and an interrupt request signal (INTAD) is generated at the same time. User's Manual U14665EJ4V0UD 359 CHAPTER 12 A/D CONVERTER (1) A/D conversion by hardware start A/D conversion is on standby if bit 6 (TRG) and bit 7 (ADCS) of A/D converter mode register 1 (ADM1) are set to 1. When an external trigger signal is input, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal. When the A/D conversion has been completed, the result of the conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has been started and completed, conversion is not started again unless a new external trigger signal is input. If data with ADCS set to 1 is written to ADM during A/D conversion, the conversion under execution is stopped, and the A/D converter stands by until a new external trigger signal is input. If the external trigger signal is input, A/D conversion is executed again from the beginning. If data with ADCS set to 0 is written to ADM1 during A/D conversion, the conversion is immediately stopped. Figure 12-6. A/D Conversion by Hardware Start (with Falling Edge Specified) External trigger input signal Rewriting ADS ADCS = 1, TRG = 1 Standby status Standby status Rewriting ADS ADCS = 1, TRG = 1 Standby status A/D conversion ANIn ANIn ANIn ANIm ANIm ANIm ADCR ANIn ANIn ANIn ANIm ANIm INTAD Remarks 1. 2. n = 0, 1, ..., 11 m = 0, 1, ..., 11 360 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (2) A/D conversion by software start If bit 6 (TRG) of A/D converter mode register 1 (ADM1) is set to 0 and bit 7 (ADCS) is set to 1, the A/D converter starts converting the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) into a digital signal. When the A/D conversion has been completed, the result of the conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once A/D conversion has been started and completed, the next conversion is started immediately. A/D conversion is repeated until new data is written to ADS. If ADS is rewritten during A/D conversion, the conversion under execution is stopped, and conversion of the newly selected analog input channel is started. If data with ADCS set to 0 is written to ADM1 during A/D conversion, the conversion is immediately stopped. Figure 12-7. A/D Conversion by Software Start Rewriting ADS ADCS = 1, TRG = 0 Rewriting ADS ADCS = 1, TRG = 0 ADCS = 0 A/D conversion ANIn ANIn ANIn Conversion stopped. Conversion result does not remain. ANIm ANIm Stopped ADCR ANIn ANIn ANIm INTAD Remarks 1. 2. n = 0, 1, ..., 11 m = 0, 1, ..., 11 User's Manual U14665EJ4V0UD 361 CHAPTER 12 A/D CONVERTER 12.5 Low Power Consumption Mode The V850/SF1 features a function that can cut or connect the current between ADCVDD and the series resistor string. Switching can be performed by setting A/D converter mode register 2 (ADM2). When not using the A/D converter, cut off the tap selector (a function to reduce current) from the voltage supply block (ADCVDD) while A/D conversion is stopped (ADCS = 0) to cut the current consumption. * Set the ADPS bit of A/D converter mode register 1 (ADM1) to 1. * Set the IEAD bit of A/D converter mode register 2 (ADM2) to 0. When the ADPS bit is reset to 0 (comparator on), stabilization time (5 s max.) is required before starting A/D conversion. Therefore, secure a wait of at least 5 s by software. 12.6 Cautions (1) Current consumption in standby mode The A/D converter stops operation in the IDLE/STOP mode (it can be operated in the HALT mode). At this time, the current consumption of the A/D converter can be reduced by stopping the conversion (by resetting bit 7 (ADCS) of A/D converter mode register 1 (ADM1) to 0). (2) Input range of ANI0 to ANI11 Keep the input voltage of the ANI0 through ANI11 pins to within the rated range. If a voltage greater than ADCVDD or lower than ADCGND (even within the range of the absolute maximum ratings) is input to a channel, the converted value of the channel becomes undefined. Moreover, the values of the other channels may also be affected. (3) Conflict <1> Conflict between writing A/D conversion result register (ADCR) and reading ADCR at end of conversion Reading ADCR takes precedence. After ADCR has been read, a new conversion result is written to ADCR. <2> Conflict between writing ADCR and external trigger signal input at end of conversion The external trigger signal is not input during A/D conversion. Therefore, the external trigger signal is not accepted while writing ADCR. <3> Conflict between writing of ADCR and writing A/D converter mode register 1 (ADM1) or analog input channel specification register (ADS) When ADM1 or ADS is written immediately after ADCR is written following the end of A/D conversion, an undefined value is stored in the ADCR register, so the conversion result is not guaranteed. 362 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (4) Countermeasures against noise To keep the resolution of 10 bits, prevent noise from being superimposed on the ANI0 to ANI11 pins. The higher the output impedance of the analog input source, the heavier the influence of noise. To lower noise, connecting an external capacitor follows is recommended. Figure 12-8. Handling of Analog Input Pin Clamp with diode with a low VF (0.3 V MAX.) if noise higher than ADCVDD or lower than ADCGND may be generated. VDD0 ADCVDD C = 100 to 1000 pF ADCGND GND0 (5) ANI0 to ANI11 The analog input (ANI0 to ANI11) pins are also used as port pins. When executing A/D conversion with any of ANI0 to ANI11 selected, do not execute an instruction that inputs data to a port during conversion; otherwise, the resolution may drop. If a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal, the expected A/D conversion result may not be obtained because of the influence of coupling noise. Therefore, do not apply a pulse to adjacent pins. User's Manual U14665EJ4V0UD 363 CHAPTER 12 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the analog input channel specification register (ADS) are changed. If the analog input pin is changed during conversion, therefore, the result of the A/D conversion of the preceding analog input signal and the conversion end interrupt request flag may be set immediately before ADS is rewritten. If ADIF is read immediately after ADS has been rewritten, it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet. When stopping A/D conversion and then resuming, clear ADIF before resuming conversion. Figure 12-9. A/D Conversion End Interrupt Generation Timing Rewriting ADS (ANIn conversion starts) Rewriting ADS (ANIm conversion starts) ADIF is set but conversion of ANIm is not completed. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm INTAD Remarks 1. 2. n = 0, 1, ..., 11 m = 0, 1, ..., 11 364 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (7) ADCVDD pin The ADCVDD pin is the power supply pin of the analog circuit, and also supplies power to the input circuit of ANI0 to ANI11. Even in an application where a back-up power supply is used, therefore, be sure to apply the same voltage as the VDD0 pin to the ADCVDD pin as shown below. Figure 12-10. Handling of ADCVDD Pin VDD0 ADCVDD Main power supply Back-up capacitor GND0 ADCGND (8) Reading A/D converter result register (ADCR) Writing to A/D converter mode register 1 (ADM1) and analog input channel specification register (ADS) may cause the ADCR contents to be undefined. Therefore, read the A/D conversion result during an A/D conversion operation (ADCS = 1). Incorrect conversion results may be read out at timings other than the above. 12.7 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREF - 0)/100 = AVREF/100 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. User's Manual U14665EJ4V0UD 365 CHAPTER 12 A/D CONVERTER (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 12-11. Overall Error 1......1 Ideal line Digital output Overall error 0......0 0 Analog input AVREF (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 12-12. Quantization Error 1......1 Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREF 366 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. Figure 12-13. Zero-Scale Error 111 Digital output (Lower 3 bits) Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 AVREF Analog input (LSB) (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1......110 to 1......111. Figure 12-14. Full-Scale Error Full-scale error Digital output (Lower 3 bits) 111 100 011 010 000 0 AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB) User's Manual U14665EJ4V0UD 367 CHAPTER 12 A/D CONVERTER (6) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 12-15. Differential Linearity Error 1......1 Ideal 1LSB width Digital output Differential linearity error 0......0 0 Analog input AVREF (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 12-16. Integral Linearity Error 1......1 Ideal line Digital output 0......0 0 Integral linearity error AVREF Analog input (8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. 368 User's Manual U14665EJ4V0UD CHAPTER 12 A/D CONVERTER (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 12-17. Sampling Time Sampling time Conversion time User's Manual U14665EJ4V0UD 369 CHAPTER 13 DMA FUNCTIONS 13.1 Functions The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA requests sent from on-chip peripheral hardware (such as a serial interface, timer, or A/D converter). This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units. The maximum number of transfers is 256 (when transferring data in 8-bit units). After a DMA transfer has occurred a specified number of times, DMA transfer completion interrupt (INTDMA0 to INTDMA5) requests are output individually from the various channels. The priority levels of the DMA channels are fixed as follows for simultaneous generation of multiple DMA transfer requests. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 13.2 Transfer Completion Interrupt Request After a DMA transfer has occurred a specified number of times and the TCn bit in corresponding DMA channel control registers 0 to 5 (DCHC0 to DCHC5) has been set to 1, a DMA transfer completion interrupt request (INTDMA0 to INTDMA5) to the interrupt controller occurs in each channel. 370 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS 13.3 Configuration Figure 13-1. DMA Block Diagram DMA transfer trigger (INT signal) DMA transfer request control DMA peripheral I/O address register n (DIOAn) DMA trigger expansion register (DMAS) DMA byte count register n (DBCn) Channel control DMA internal RAM address register n (DRAn) DMA channel control register n (DCHCn) CPU DMA transfer acknowledge signal INTDMAn Interface control Internal RAM Internal bus Peripheral I/O register (1) DMA transfer request control block The DMA transfer request control block generates a DMA transfer request signal for the CPU when the DMA transfer start factor (INT signal) specified by DMA channel control register n (DCHCn) and the DMA trigger expansion register (DMAS) is input. When the DMA transfer request signal is acknowledged, the CPU generates a DMA transfer acknowledge signal for the channel control block and interface control block after the current CPU processing has finished. (2) Channel control block The channel control block distinguishes the DMA transfer channel (DMA0 to DMA5) to be transferred and controls the internal ROM, peripheral I/O addresses, and access cycles (internal RAM: 1 clock, peripheral I/O register: 3 clocks) set by the peripheral I/O registers of the channel to be transferred, the transfer direction, and the transfer count. In addition, it also controls the priority order when two or more DMAn transfer triggers (INT signals) are generated simultaneously. User's Manual U14665EJ4V0UD 371 CHAPTER 13 DMA FUNCTIONS 13.4 Control Registers Remark n = 0 to 5 in section 13.4. (1) DMA peripheral I/O address registers 0 to 5 (DIOA0 to DIOA5) These registers are used to set the peripheral I/O register address for DMA channel n. These registers can be read/written in 16-bit units. After reset: Undefined R/W Address: DIOA0 DIOA1 DIOA2 15 DIOAn 0 14 0 13 0 12 0 11 0 10 0 9 IOAn9 to IOAn1 FFFFF180H FFFFF190H FFFFF1A0H DIOA3 DIOA4 DIOA5 FFFFF1B0H FFFFF1C0H FFFFF1D0H 1 0 0 Caution The following peripheral I/O registers must not be set. P4, P5, P6, P9, P11, PM4, PM5, PM6, PM9, PM11, MM, DWC, BCC, PSC, PCC, SYS, PRCMD, DIOAn, DRAn, DBCn, DCHCn, CORCN, CORRQ, CORADn, interrupt control register (xxICn), ISPR, POCS, VM45C, FCAN register (see CHAPTER 18) (2) DMA internal RAM address registers 0 to 5 (DRA0 to DRA5) These registers set DMA channel n internal RAM addresses. Since each product has a different internal RAM capacity, the internal RAM areas that are usable for DMA differ depending on the product. The internal RAM areas that can be set in the DRAn register for each product are shown below. Table 13-1. Internal RAM Area Usable for DMA Product Internal RAM Capacity RAM Size Usable in DMA 12 KB 16 KB xxFFC000H to xxFFEFFFH xxFFB000H to xxFFEFFFH RAM Area Usable in DMA PD703075AY, 703076AY PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y 12 KB 16 KB An address is incremented after each transfer is completed, when the DADn bit of the DCHCn register is 0. The incrementation value is "1" for 8-bit transfer and "2" for 16-bit transfer. These registers can be read/written in 16-bit units. After reset: Undefined R/W Address: DRA0 DRA1 DRA2 15 DRAn 0 14 0 13 RAn13 to RAn0 FFFFF182H FFFFF192H FFFFF1A2H DRA3 DRA4 DRA5 FFFFF1B2H FFFFF1C2H FFFFF1D2H 0 372 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS The following shows the correspondence between the DRAn setting value and the internal RAM area. (a) PD703075AY, 703076AY Set the DRAn register to a value in the range of 0000H to 2FFFH. Setting the values in the range of 3000H to 3FFFH is prohibited. Figure 13-2. Correspondence Between DRAn Setting Value and Internal RAM (16 KB) (DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH On-chip peripheral I/O area (2FFFH) Internal RAM area 12 KB (usable for DMA) xxFFC000H xxFFBFFFH (0000H) Access-prohibited area xxFF8000H xxFF7FFFH Expansion ROM area Caution Remark Do not set odd addresses for 16-bit transfer (DCHCn register DSn =1). The DRAn register setting values are in the parentheses. User's Manual U14665EJ4V0UD 373 CHAPTER 13 DMA FUNCTIONS (b) PD703078AY, 703078Y, 703079AY, 703079Y, 70F3079AY, 70F3079Y Set the DRAn register to a value in the range of 0000H to 2FFFH or 3000H to 3FFFH. Figure 13-3. Correspondence Between DRAn Setting Value and Internal RAM (16 KB) (DRAn setting value) xxFFFFFFH xxFFF000H xxFFEFFFH On-chip peripheral I/O area (2FFFH) Internal RAM area xxFFC000H xxFFBFFFH xxFFB000H xxFFAFFFH 16 KB (usable for DMA) (0000H) (3FFFH) (3000H) Access-prohibited area xxFF8000H xxFF7FFFH Expansion ROM area Caution Remark Do not set odd addresses for 16-bit transfer (DCHCn register DSn = 1). The DRAn register setting values are in parentheses. 374 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS (3) DMA byte count registers 0 to 5 (DBC0 to DBC5) These are 8-bit registers that are used to set the number of transfers for DMA channel n. The remaining number of transfers is retained during DMA transfer. A value of 1 is decremented once per transfer if the transfer is a byte (8-bit) transfer, and a value of 2 is decremented once per transfer if the transfer is a 16-bit transfer. Transfer ends when a borrow operation occurs. Accordingly, "number of transfers - 1" should be set for byte (8-bit) transfers and "(number of transfers - 1) x 2" should be set for 16-bit transfers. These registers can be read/written in 8-bit units. After reset: Undefined R/W Address: DBC0 DBC1 DBC2 7 DBCn BCn7 6 BCn6 5 BCn5 4 BCn4 FFFFF184H FFFFF194H FFFFF1A4H 3 BCn3 DBC3 DBC4 DBC5 FFFFF1B4H FFFFF1C4H FFFFF1D4H 2 BCn2 1 BCn1 0 BCn0 Caution Values set to bit 0 are ignored during 16-bit transfer. (4) DMA trigger expansion register (DMAS) This is an 8-bit register for expanding the triggers that start DMA. The DMA trigger is decided according to the combination of TTYPn1 and TTYPn0 of the DCHCn register. For setting bits DMAS2 to DMAS0, refer to (6) Trigger settings. This register can be read/written in 8-bit or 1-bit units. After reset: 00H 7 DMAS 0 R/W 6 0 Address: 5 0 FFFFF38EH 4 0 3 0 2 DMAS2 1 DMAS1 0 DMAS0 User's Manual U14665EJ4V0UD 375 CHAPTER 13 DMA FUNCTIONS (5) DMA channel control registers 0 to 5 (DCHC0 to DCHC5) These registers are used to control the DMA transfer operation mode for DMA channel n. Refer to (6) Trigger settings for the TTYPn1 and TTYPn0 bit settings. These registers can be read/written in 8-bit or 1-bit units. After reset: 00H R/W Address: DCHC0 DCHC1 DCHC2 FFFFF186H FFFFF196H FFFFF1A6H 4 3 TTYPn0 DCHC3 FFFFF1B6H DCHC4 FFFFF1C6H DCHC5 FFFFF1D6H 2 TDIRn 1 DSn 0 ENn 7 DCHCn TCn 6 0 5 DDADn TTYPn1 TCn 0 1 Not completed Completed DMA transfer completed/not completed Note 1 DDADn 0 1 Incremented Address is fixed Internal RAM address count direction control TDIRn 0 1 Transfer direction control between peripheral I/Os and internal RAM From internal RAM to peripheral I/Os From peripheral I/Os to internal RAM Note 2 DSn 0 1 8-bit transfer 16-bit transfer Control of transfer data size for DMA transfer Note 2 ENn 0 1 Disabled Control of DMA transfer enable/disable status Note 3 Enabled (reset to 0 after DMA transfer is complete) Notes 1. TCn (n = 0 to 5) is set to 1 when a specified number of transfers are complete, and is cleared to 0 when a write instruction is executed. 2. Make sure that the transfer format conforms to the peripheral I/O register specifications (accessenabled data size, read/write, etc.) for the DMA peripheral I/O address register (DIOAn). 3. After the specified number of transfers is complete, this bit is cleared to 0. 376 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS (6) Trigger settings The DMA trigger is set using bits 2 to 0 (DMAS2 to DMAS0) of the DMA trigger expansion register (DMAS) in combination with bits 4 and 3 (TTYPn1, TTYPn0) of DMA channel control registers 0 to 5 (DCHC0 to DCHC5). Table 13-1 shows the DMA trigger settings. Cautions 1. If the interrupt that is the DMA trigger is not masked, interrupt servicing is performed each time DMA starts. To prevent interrupt servicing from being performed, mask the interrupt. 2. If an interrupt source is generated asynchronously to the internal system clock, do not set the interrupt source as a multiple DMA trigger (for example, when the serial interface is operated on external clock input). If set, the priority order of DMA may be reversed. Table 13-2. Trigger Settings Channel n 0 DMAS2 x DMAS1 x DMAS0 x TTYPn1 0 0 1 1 1 x x 0 1 x 0 0 0 1 1 2 x 0 1 x x 0 0 0 1 1 3 0 1 x x x 0 0 0 1 1 4 x x x 0 0 1 1 5 x x x 0 0 1 1 TTYPn0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 DMA Transfer Trigger Settings INTCSI0/INTIIC0 INTCSI1/INTSR0 INTAD INTTM00 INTCSI0/INTIIC0 INTCSI1/INTSR0 INTST0 INTP0 INTTM10 INTCSI4 INTCSI3/INTSR1 INTP6 Setting prohibited INTAD INTTM3 INTCSI3/INTSR1 INTTM5 Setting prohibited INTTM4 INTST1 INTCSI4 INTAD INTTM2 INTCSI3/INTSR1 INTCSI4 INTTM70 INTTM6 Remarks 1. DMAS2 to DMAS0: Bits 2 to 0 of the DMA trigger expansion register (DMAS) 2. TTYPn1, TTYPn0: Bits 4 and 3 of DMA channel control register n (DCHCn) 3. x: don't care User's Manual U14665EJ4V0UD 377 CHAPTER 13 DMA FUNCTIONS 13.5 Operation When a DMA transfer request is generated during CPU processing, DMA transfer is started after the current CPU processing has finished. Regardless of the transfer direction, 4 CPU clocks (fCPU) are required for one DMA transfer. The 4 CPU clocks are divided as follows. * Internal RAM access: 1 clock * Peripheral I/O access: 3 clocks After one DMA transfer (8/16 bits) ends, control always shifts to the CPU processing. A DMA transfer operation timing chart is shown below. Figure 13-4. DMA Transfer Operation Timing fCPU DMA transfer processing signal DMA transfer acknowledge signal Processing format CPU processing DMA transfer processing CPU processing Access destination for transfer from internal RAM to peripheral I/O RAM Peripheral I/O Access destination for transfer from peripheral I/O to internal RAM Peripheral I/O RAM INTDMAn occurs when a DBCn register borrow occurs If two or more DMA transfer requests are generated simultaneously, the DMA transfer requests are executed in the following priority order: DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5. While a higher priority DMA transfer request is being executed, the lower priority DMA transfer requests are held pending. After the higher priority DMA transfer ends, control always shifts to the CPU processing once, and then the lower priority DMA transfer is executed. The processing when the transfer requests DMA0 to DMA5 are generated simultaneously is shown below. 378 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS Figure 13-5. Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously CPU DAM0 CPU DAM1 CPU DAM2 CPU DAM3 CPU DAM4 CPU DAM5 CPU processing processing processing processing processing processing processing processing processing processing processing processing processing Transfer requests DMA0 to DMA5 are generated simultaneously DMA operation stops only in the IDLE/STOP mode. In the HALT mode, DMA operation continues. DMA also operates during the bus hold period and after access to the external memory. 13.6 Cautions When using the DMA function, if all the following conditions are met during the EI state (interrupt enabled state), two interrupts occur when only one interrupt would occur normally. [Occurrence conditions] (i) (ii) A bit manipulation instruction (SET1, CLR1, NOT1, TST1) was executed to the interrupt request flag (xxIFn) of the interrupt control register (xxICn). An interrupt was processed by hardware at the same register as the register used in (i). xx: Identification name of peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) For example, when using the DMA function, if an unmasked INTCSI0 interrupt occurs during bit manipulation of the interrupt request flag (CSIF0) of the CSIC0 register by the CLR1 instruction, INTCSI0 interrupt servicing occurs twice. Under such conditions, because the interrupt request flag (xxIF) is not cleared (0) by hardware when the interrupt servicing is acknowledged, the interrupt servicing is executed again after RETI instruction execution (interrupt servicing restoration). Therefore, use the DMA function under either of the following conditions. [Usage conditions] (i) (ii) When bit manipulation is executed for the interrupt control register (xxICn), the DI instruction must be executed before manipulation and the EI instruction must be executed after manipulation. The interrupt request flag (xxIFn) must be cleared (0) at the start of the interrupt routine. When the DMA function is not used, execution of (i) or (ii) is not necessary. xx: Identification name of peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) Remark Caution Remark User's Manual U14665EJ4V0UD 379 CHAPTER 13 DMA FUNCTIONS Figure 13-6. When Interrupt Servicing Occurs Twice During DMA Operation (1/2) (a) Normal interrupt servicing Main routine Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0). EI Interrupt request RETI (b) Interrupt servicing when interrupt servicing occurs twice Main routine EI Bit manipulation instruction to xxIFn Interrupt request Since the interrupt request flag (xxIFn) remains 1, the interrupt is serviced again. Interrupt servicing routine Interrupt request flag (xxIFn) is not cleared and remains 1. RETI Interrupt request flag (xxIFn) is cleared (0). RETI Remark xx: Identification name of peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 380 User's Manual U14665EJ4V0UD CHAPTER 13 DMA FUNCTIONS Figure 13-6. When Interrupt Servicing Occurs Twice During DMA Operation (2/2) (c) Countermeasure (usage condition (i)) Main routine EI DI Bit manipulation instruction to xxIFn Interrupt request EI The interrupt is serviced in the EI state (interrupt enable state) (the interrupt is not serviced immediately after bit manipulation instruction execution). Interrupt servicing routine Interrupt request flag (xxIFn) is cleared (0). RETI (d) Countermeasure (usage condition (ii)) Main routine EI Bit manipulation instruction to xxIFn Interrupt request EI Interrupt servicing routine Interrupt request flag (xxIFn) is not cleared (0) and remains 1. xxIFn is cleared (0) at the start of the interrupt servicing routine RETI Remark xx: Identification name of peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) User's Manual U14665EJ4V0UD 381 CHAPTER 14 RESET FUNCTION 14.1 General There are two methods used to generate a reset signal. (1) External reset by RESET signal input (2) Internal reset by power-on-clear (POC) (1) External reset by RESET signal input When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period, although oscillation of the subclock continues. When the input at the RESET pin changes from low level to high level, the reset status is released and the CPU resumes program execution after the oscillation stabilization time has elapsed (PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY: 218/fXX, PD703078Y, 703079Y, 70F3079Y: 221/fXX). The contents of the various registers should be initialized within the program as necessary. An on-chip noise eliminator uses analog delay to prevent noise-related malfunction at the RESET pin. (2) Internal reset by power-on-clear (POC) When either of the following conditions is satisfied, a system reset is performed by power-on-clear. * * * When the supply voltage is less than 3.3 VNote at power application When the supply voltage is less than 2.1 VNote in STOP mode When the supply voltage becomes less than 3.3 VNote (other than when STOP mode is selected) When any one of the conditions above is satisfied, a system reset is performed and the various on-chip hardware devices are initialized. In addition, the main clock stops oscillation during the reset period, although the subclock continues oscillation. The power-on-clear reset is released after the power supply voltage reaches a certain voltage and the system starts program execution after the oscillation stabilization time has elapsed (PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY: 218/fXX, PD703078Y, 703079Y, 70F3079Y: 221/fXX). Note The voltage values are maximum values; a system reset is actually performed at a lower voltage. 382 User's Manual U14665EJ4V0UD CHAPTER 14 RESET FUNCTION 14.2 Pin Operations During the system reset period, almost all pins are set to high impedance (except for RESET, X2, CPUREG, VDD0, ADCVDD, ADCGND, PORTVDD, PORTGND, GND0, GND1, GND2, and VPP/IC). Accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor at each pin. If such a resistor is not attached, high impedance will be set for these pins, which could damage the data in memory devices. Likewise, make sure the pins are handled so as to prevent such effects at the signal outputs of onchip peripheral I/O functions and output ports. Figure 14-1. Timing of Reset by RESET Input Hi-Z X1 Oscillation stabilization time RESET Analog delay Analog delay Analog delay Internal system reset signal Eliminated as noise Reset is acknowledged Reset is canceled Note Note 131 ms (@16 MHz operation): PD703078Y, 703079Y, 70F3079Y 16.4 ms (@16 MHz operation): PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY User's Manual U14665EJ4V0UD 383 CHAPTER 14 RESET FUNCTION Figure 14-2. Timing of Reset by Power-on-Clear (a) At power application X1 Reset period (oscillation stopped) VDD Power-on-clear voltage Internal reset signal I/O port pin Hi-Z Oscillation stabilization time wait Normal operation (reset processing) (b) In STOP mode X1 Hi-Z STOP instruction execution Reset period Normal Stop status (oscillation operation (oscillation stopped) stopped) Oscillation stabilization time wait Normal operation (reset processing) VDD Internal Power-on-clear voltage in STOP mode reset signal I/O port pin Power-on-clear voltage in normal operation Hi-Z (c) In normal operating mode (including HALT mode) X1 Normal operation VDD Power-on-clear voltage Internal reset signal I/O port pin Hi-Z Hi-Z Reset period (oscillation stopped) Oscillation stabilization time wait Normal operation (reset processing) Remark Refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS for power-on-clear voltage. 384 User's Manual U14665EJ4V0UD CHAPTER 14 RESET FUNCTION 14.3 Power-on-Clear Operation The V850/SF1 includes a power-on-clear circuit (POC), through which low-voltage detection and VDD0 pin voltage detection (4.2 0.3 V) can be performed using the POC status register (POCS). (1) POC status register (POCS) When a power-on-clear is generated, bit 0 of the POCS register is set to 1. In addition, if the voltage level at the VDD0 pin is less than 4.2 0.3 V, bit 1 of the POCS register is set to 1, thus enabling detection of a voltage level of less than 4.2 0.3 V at the VDD0 pin. In the case of a reset generated by the RESET pin, however, the POCM and VM45 bits retain their previous statuses. A low voltage state can be detected by reading the POCS register following reset cancellation. The POCS register is read-only, using an 8-bit memory manipulation instruction. This register is reset when read. After reset: Retained 7 POCS 0 Note R 6 0 Address: FFFFF07AH 5 0 4 0 3 0 2 0 1 VM45 0 POCM POCM 0 1 Detection of power-on-clear generation status Power-on-clear not generated Power-on-clear reset generated VM45 0 1 Detection of VDD0 pin voltage level VDD0 pin voltage of less than 4.5 V not detected VDD0 pin voltage of less than 4.5 V detected Note This value is 03H only after a power-on-clear reset; it is not initialized by a reset from the RESET pin. User's Manual U14665EJ4V0UD 385 CHAPTER 14 RESET FUNCTION (2) VM45 control register (VM45C) The detection status (detected/undetected) according to the POCS register's VM45 bit can be output (monitored) at the VM45/P34 pin via control by the VM45C register. After reset: 00H 7 VM45C 0 R/W 6 0 Address: FFFFF07CH 5 0 4 0 3 0 2 0 1 VM45C1 0 VM45C0 VM45C1 0 1 VM45 (VDD0 4.5 V monitor) output enabled/disabled VM45 output at VM45/P34 pin disabled (port function) VM45 output at VM45/P34 pin enabled Note VM45C0 0 1 VM45 (VDD0 4.5 V monitor) output selection High-level output when VM45 detected Low-level output when VM45 detected Note When using P34 as an alternate-function pin, it is necessary to set the PM34 bit of the port 3 mode register (PM3) to 0 (output mode), or the P34 bit of port 3 (P3) to 0 (0 output). 386 User's Manual U14665EJ4V0UD CHAPTER 15 REGULATOR 15.1 Outline The V850/SF1 incorporates a regulator to realize a 5 V single power supply, low power consumption, and to reduce noise. This regulator supplies a voltage obtained by stepping down the VDD power supply voltage to oscillation blocks and on-chip logic circuits (excluding the A/D converter and output buffers). The regulator output voltage is set to 3.0 V. Refer to 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins for the power supply corresponding to each pin. Figure 15-1. Regulator PORTVDD-system I/O buffer PORTVDD Internal digital circuit (3.0 V) Flash memory Main/sub oscillators CPUREG Bidirectional level shifter Regulator VDD0 VPP 1.0 F (Recommended) A/D converter 4.5 to 5.5 V ADCVDD 15.2 Operation The regulator of the V850/SF1 operates in every mode (STOP, IDLE, HALT). For stabilization of regulator outputs, connect an electrolytic capacitor of about 1.0 F to the CPUREG pin. User's Manual U14665EJ4V0UD 387 CHAPTER 16 ROM CORRECTION FUNCTION Remark n = 0 to 3 in CHAPTER 16. 16.1 General The ROM correction function provided in the V850/SF1 is a function that replaces part of a program in the mask ROM with a program in the internal RAM. First, the instruction of the address where the program replacement should start is replaced with the JMP r0 instruction and the program is instructed to jump to 00000000H. The correction request register (CORRQ) is then checked. At this time, if the CORRQn flag is set (1), program control shifts to the internal RAM after being made to jump to the internal RAM area by an instruction such as a jump instruction. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction function. Up to four correction addresses can be specified. Cautions 1. The ROM correction function cannot be used for the data in the internal ROM; it can only be used for instruction codes. If the ROM correction is carried out on data, that data will replace the instruction code of the JMP r0 instruction. 2. ROM correction for instructions that access the CORCN, CORRQ, or CORAD0 to CORAD3 registers is prohibited. Figure 16-1. Block Diagram of ROM Correction Instruction address bus Correction address register n (CORADn) JMP r0 instruction generation Comparator ROM (1 MB area) Correction control register (CORCNn bit) S R Q Instruction replacement Instruction data bus 0 clear instruction Correction request register (CORRQn bit) 388 User's Manual U14665EJ4V0UD CHAPTER 16 ROM CORRECTION FUNCTION 16.2 ROM Correction Peripheral I/O Registers 16.2.1 Correction control register (CORCN) CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction when the correction address matches the fetch address. Whether match detection by a comparator is enabled or disabled can be set for each channel. CORCN can be set by an 8-bit or 1-bit memory manipulation instruction. After reset: 00H 7 CORCN 0 R/W 6 0 Address: FFFFF36CH 5 0 4 0 3 COREN3 2 COREN2 1 COREN1 0 COREN0 CORENn 0 1 CORADn register and fetch address match detection control Match detection disabled Match detection enabled 16.2.2 Correction request register (CORRQ) CORRQ saves the channel in which ROM correction occurred. The JMP r0 instruction makes the program jump to 00000000H after the correction address matches the fetch address. At this time, the program can judge the following cases by reading CORRQ. * Reset input: * ROM correction generation: CORRQ = 00H CORRQn bit = 1 * Branch to 00000000H by user program: CORRQ = 00H After reset: 00H 7 CORRQ 0 R/W 6 0 Address: FFFFF36EH 5 0 4 0 3 CORRQ3 2 CORRQ2 1 CORRQ1 0 CORRQ0 CORRQn 0 1 Note Channel n ROM correction request flag No ROM correction request occurred. ROM correction request occurred. Note The CORRQn bit is cleared by using an instruction that writes 0. User's Manual U14665EJ4V0UD 389 CHAPTER 16 ROM CORRECTION FUNCTION 16.2.3 Correction address registers 0 to 3 (CORAD0 to CORAD3) CORADn sets the start address of an instruction to be corrected (correction address) in the ROM. Up to four points of the program can be corrected at once since the V850/SF1 has four correction address registers (CORADn). Since the ROM capacity differs depending on the product, set the correction address in the following range. PD703075AY, 703076AY (128 KB): 00000000H to 0001FFFEH PD703078AY, 703078Y, 703079AY, 703079Y (256 KB): 00000000H to 0003FFFEH Bits 0 and 18 to 31 should be fixed to 0. After reset: 00000000H R/W Address: CORAD0: FFFFF370H CORAD1: FFFFF374H 31 18 17 CORAD2: FFFFF378H CORAD3: FFFFF37CH 1 0 CORADn Fixed to 0 Correction address 0 390 User's Manual U14665EJ4V0UD CHAPTER 16 ROM CORRECTION FUNCTION Figure 16-2. ROM Correction Operation and Program Flow START(reset vector) CORRQn = 0? Yes Microcontroller initialization No Clears CORRQn flag. JMP channel n correct code address The address of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM. Executes correction program code Data for ROM correction setting is loaded from an external memory into the internal RAM to initialize ROM correction function. If there is a correction code, it is loaded in the internal RAM. Executes internal ROM program Jumps to internal ROM No Correction address? Yes CORENn = 1? Yes CORRQn flag set No JMP r0 : Executed by a program stored in the internal ROM : Executed by a program stored in the internal RAM : Executed by the ROM correction function Caution Check the ROM correction generation from the vector table with a high interrupt level when executing ROM correction during a vector interrupt routine. If an interrupt conflicts with ROM correction, processing is branched to an interrupt vector, where, if ROM correction is being re-executed, CORRQn is set (1) again and multiple CORRQn flags are set (1). The channel for which ROM correction is to be executed is determined by the interrupt level. User's Manual U14665EJ4V0UD 391 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) The PD70F3079AY and 70F3079Y are the flash memory versions of the V850/SF1 and incorporate a 256 KB flash memory. In the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock in the same way as in the mask ROM version. Caution There are differences in noise immunity and noise radiation between flash memory versions and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions. Writing to flash memory can be performed with memory mounted on the target system (on board). A dedicated flash programmer is connected to the target system to perform writing. The following can be considered the development environment and applications in which flash memory is used. * Software can be altered after the V850/SF1 is solder-mounted on the target system. * Small scale production of various models is made easier by differentiating software. * Data adjustment in starting mass production is made easier. 17.1 Features * 4-byte/1-clock access (in instruction fetch access) * All area batch erase/area unit erase * Communication via serial interface with the dedicated flash programmer * Erase/write voltage: VPP = 7.8 V * On-board programming * Flash memory programming via self-rewrite in area (128 KB) units is possible 17.1.1 Erasing unit This product has following two erasure units. (a) All area batch erase The area of xx000000H to xx03FFFFH can be erased at the same time. The erasure time is 4.0 s. (b) Area erase Erasure can be performed in area units (there are two 128 KB unit areas). The erasure time is 2.0 s for each area. Area 0: Area 1: The area of xx000000H to xx01FFFFH (128 KB) is erased The area of xx020000H to xx03FFFFH (128 KB) is erased 17.1.2 Write/read time The write/read time is shown below. Write time: 20 s/byte Read time: 62.5 ns (cycle time) 392 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.2 Writing with Flash Programmer Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850/SF1 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) Off-board programming Writing to flash memory is performed by the dedicated program adapter (FA Series), etc., before mounting the V850/SF1 on the target system. Remark The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd. User's Manual U14665EJ4V0UD 393 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) Figure 17-1. Example of Wiring of Adapter for Flash Programming (FA-100GC-8EU) (1/2) VD D D N G D VD D N G 71 66 PD70F3079AY, PD70F3079Y 38 95 96 Connect to GND. Connect to VDD. 29 Note 6 D N G D VD 8 9 10 11 13 22 23 24 25 G N D VD D SI SO SCK X1 X2 /RESET VPP RESERVE/HS Note The PD70F3079AY and 70F3079Y cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3/PG-FP4). Supply the clock by creating an oscillator on the flash writing adapter (broken-line portion). An example of the oscillator is shown below. Example X1 X2 394 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) Figure 17-1. Example of Wiring of Adapter for Flash Programming (FA-100GC-8EU) (2/2) Remarks 1. Handle the pins not described above in accordance with the recommended connection of unused pins (refer to 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins). When connecting via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 100-pin plastic LQFP package. 3. This diagram shows the wiring when using CSI supporting handshake. Table 17-1. Table for Wiring of Adapter for PD70F3079AY and 70F3079Y Flash Programming (FA-100GC-8EU) Flash Programmer (PG-FP3/PG-FP4) When Using CSI0 + HS Pin Name SI/RxD SO/TxD SCK CLK Note 1 When Using CSI0 Pin Name P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP Unnecessary 24 23 25 Unnecessary 11 13 Unnecessary Pin No. When Using UART0 Pin Name P14/SO1/TXD0 P13/SI1/RXD0 Unnecessary Unnecessary RESET IC/VPP Unnecessary 28 27 Unnecessary Unnecessary 11 13 Unnecessary Pin No. Pin No. 24 23 25 Unnecessary 11 13 29 Input Receive signal P11/SO0 P10/SI0/SDA0 P12/SCK0/SCL0 Unnecessary RESET IC/VPP P15/SCK1/ASCK 0 Output Transmit signal Output Transfer clock - Unused /RESET VPP HS Output Reset signal Output Writing voltage Input Handshake signal of CSI0 + HS communication VDD Note 2 - VDD voltage generation VDD0 PORTVDD ADCVDD 8 66 95 6 22 38 71 96 VDD0 PORTVDD ADCVDD GND0 GND1 GND2 PORTGND0 ADCGND 8 66 95 6 22 58 71 96 VDD0 PORTVDD ADCVDD GND0 GND1 GND2 PORTGND ADCGND 8 66 95 6 22 38 71 96 GND - Ground GND0 GND1 GND2 PORTGND ADCGND Notes 1. The PD70F3079AY and 70F3079Y cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3/PG-FP4). Supply the clock by creating an oscillator on the flash writing adapter (FA-100GC-8EU). For an example of the oscillator, refer to Figure 17-1 Example of Wiring of Adapter for Flash Programming (FA-100GC-8EU). 2. The PG-FP3 is provided with a VDD voltage monitoring function. User's Manual U14665EJ4V0UD 395 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850/SF1. Figure 17-2. Environment Required for Writing Programs to Flash Memory VPP XXXX YYYY Bxxxxx Cxxxxxx USB XXXX XXXXXX RS-232-C Axxxx VDD PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE VSS RESET V850/SF1 Dedicated flash programmer Host machine UART0/CSI0 A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used as the interface between the dedicated flash programmer and the V850/SF1 to perform writing, erasing, etc. A dedicated program adapter (FA Series) required for off-board writing. 396 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.4 Communication Mode Communication between the dedicated flash programmer and the V850/SF1 is performed by serial communication using UART0 or CSI0 of the V850/SF1. (1) UART0 Transfer rate: 4800 to 76800 bps Figure 17-3. Communication with Dedicated Flash Programmer (UART0) VPP VDD GND RESET Dedicated flash programmer RXD TXD VPP VDD0 GND0 to GND2 RESET TXD0 RXD0 V850/SF1 (2) CSI0 Serial clock: Up to 1 MHz (MSB first) Figure 17-4. Communication with Dedicated Flash Programmer (CSI0) VPP VDD GND RESET Dedicated flash programmer SI SO SCK VPP VDD0 GND0 to GND2 RESET SO0 SI0 SCK0 V850/SF1 User's Manual U14665EJ4V0UD 397 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) (3) CSI0 + HS Serial clock: Up to 1 MHz (MSB first) Figure 17-5. Communication with Dedicated Flash Programmer (CSI0 + HS) VPP VDD GND RESET Dedicated flash programmer SI SO SCK HS VPP VDD0 GND0 to GND2 RESET SO0 SI0 SCK0 P15 V850/SF1 The dedicated flash programmer outputs the transfer clock, and the V850/SF1 operates as a slave. When the PG-FP3 or PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850/SF1. For the details, refer to the PG-FP3/PG-FP4 User's Manual. Table 17-2. Signal Generation of Dedicated Flash Programmer (PG-FP3/PG-FP4) PG-FP3/PG-FP4 Signal Name VPP VDD Note 1 V850/SF1 Pin Function Pin Name VPP VDD0 GND0 to GND2 X1 RESET SO0/TXD0 SI0/RXD0 SCK0 P15 Measures When Connected CSI0 UART0 CSI0 + HS I/O Output I/O - - Output Input Output Output Input Writing voltage VDD voltage generation Ground Unused Reset signal Receive signal Transmit signal Transfer clock Handshake signal of CSI0 + HS GND CLK Note 2 x x x RESET SI/RxD SO/TxD SCK HS x x x Notes 1. 2. The PG-FP3 is provided with a VDD voltage monitoring function. The PD70F3079AY and 70F3079Y cannot be supplied with the clock from the CLK pin of the flash programmer (PG-FP3/PG-FP4). Supply the clock by creating an oscillator on the flash writing adapter (FA-100GC-8EU). For an example of the oscillator, refer to Figure 17-1 Example of Wiring of Adapter for Flash Programming (FA-100GC-8EU). Remark x: : Always connected Does not need to be connected 398 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, design a function on-board to switch from the normal operation mode to the flash memory programming mode. When switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset. Therefore, all the ports become output high-impedance, making pin handling necessary if the external device does not acknowledge the output high-impedance status. 17.5.1 VPP pin In the normal operation mode, 0 V is input to the VPP pin. In the flash memory programming mode, a 7.8 V writing voltage is supplied to the VPP pin. The following shows an example of the connection of the VPP pin. Figure 17-6. VPP Pin Connection Example V850/SF1 Dedicated flash programmer connection pin VPP Pull-down resistor (RVPP) 17.5.2 Serial interface pin The following shows the pins used by each serial interface. Table 17-3. Pins Used by Serial Interfaces Serial Interface CSI0 CSI0 + HS UART0 Pins Used SO0, SI0, SCK0 SO0, SI0, SCK0, P15 TXD0, RXD0 When connecting a dedicated flash programmer to a serial interface pin that is connected to other devices onboard, care should be taken to the conflict of signals and the malfunction of other devices, etc. User's Manual U14665EJ4V0UD 399 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) (1) Conflict of signals When connecting the dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to output high-impedance. Figure 17-7. Conflict of Signals (Serial Interface Input Pin) V850/SF1 Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pins In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. Therefore, isolate the signals on the other device side. (2) Malfunction of other device When connecting dedicated flash programmer (output or input) to a serial interface pin (input or output) that is connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. Figure 17-8. Malfunction of Other Device V850/SF1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850/SF1 outputs affects the other device, isolate the signal on the other device side. V850/SF1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. 400 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. dedicated flash programmer. Figure 17-9. Conflict of Signals (RESET Pin) V850/SF1 Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin Therefore, do not input signals other than the reset signals from the In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. 17.5.4 Port pin (including NMI) When the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer become output high-impedance. via resistors. 17.5.5 Other signal pins Connect X1, X2, XT1, and XT2 in the same status as that in the normal operation mode. 17.5.6 Power supply Supply the power as follows: VDD0 = PORTVDD Supply the power (ADCVDD, ADCGND, GND0 to GND2, and PORTGND) in the same way as in normal operation mode. Caution VDD of the dedicated flash programmer (PG-FP3) has a voltage monitoring function. Be sure to connect VDD0 and GND0 to GND2 to the VDD and GND of the dedicated flash programmer. If problems such as disabling the output highimpedance status should occur in the external devices connected to the port, connect them to VDD0 or GND0 to GND2 User's Manual U14665EJ4V0UD 401 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.6 Programming Method 17.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 17-10. Procedure for Manipulating Flash Memory Start Supplies RESET pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? Yes End No 17.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850/SF1 in the flash memory programming mode. When switching modes, set the VPP pin before canceling reset. When performing on-board writing, switch modes using a jumper, etc. Figure 17-11. Flash Memory Programming Mode Flash memory programming mode 7.8 V VPP 3 V 0V RESET 1 2 ... n VPP 0V 7.8 V Operation mode Normal operation mode Flash memory programming mode 402 User's Manual U14665EJ4V0UD CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 17.6.3 Selection of communication mode In the V850/SF1, a communication mode is selected by inputting pulses (16 pulses max.) to the VPP pin after switching to the flash memory programming mode. The VPP pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Table 17-4. List of Communication Mode VPP Pulse 0 3 8 Others Communication Mode CSI0 CSI0 + HS UART0 RFU Remarks V850/SF1 performs slave operation, MSB first V850/SF1 performs slave operation, MSB first Communication rate: 9600 bps (after reset), LSB first Setting prohibited Caution When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the VPP pulse. 17.6.4 Communication command The V850/SF1 communicates with the dedicated flash programmer by means of commands. The command sent from the dedicated flash programmer to the V850/SF1 is called a "command". The response signal sent from the V850/SF1 to the dedicated flash programmer is called a "response command". Figure 17-12. Communication Command Command Response command Dedicated flash programmer V850/SF1 The following shows the commands for flash memory control of the V850/SF1. All of these commands are issued from the dedicated flash programmer, and the V850/SF1 performs the various processing corresponding to the commands. User's Manual U14665EJ4V0UD 403 CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) Table 17-5. Flash Memory Control Commands Category Verify Command Name Batch verify command Function Compares the contents of the entire memory and the input data. Area verify command Compares the contents of the specified area and the input data Erase Area erase command Write back command Blank check Batch blank check command Area blank check command Data write High-speed write command Erases a specified area. Writes back the contents which is overerased. Checks the erase state of the entire memory. Checks the erase state of the specified area Writes data by the specification of the write address and the number of bytes to be written, and executes verify check. Continuous write command Writes data from the address following the highspeed write command executed immediately before, and executes verify check. System setting and control Status read out command Oscillating frequency setting command Erasure time setting command Writing time setting command Write back time setting command Baud rate setting command Silicon signature command Reset command Acquires the status of operations. Sets the oscillating frequency. Sets the erasure time of batch erase. Sets the writing time of data write. Sets the write back time. Sets the baud rate when using UART. Reads outs the silicon signature information. Escapes from each state. The V850/SF1 sends back response commands to the commands issued from the dedicated flash programmer. The following shows the response commands the V850/SF1 sends out. Table 17-6. Response Commands Response Command Name ACK (acknowledge) NAK (not acknowledge) Function Acknowledges command/data, etc. Acknowledges illegal command/data, etc. 404 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER The V850/SF1 features an on-chip FCAN (Full Controller Area Network) controller that complies with CAN specification Ver. 2.0, Part B. channel devices.) (The V850/SF1 product line includes the PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y as two-channel devices and the PD703075AY, 703078AY, and 703078Y as single- 18.1 Overview of Functions Table 18-1 presents an overview of the FCAN functions. Table 18-1. Overview of Functions Function Protocol Baud rate Data storage Description CAN Protocol Ver. 2.0 Part B active (standard and extended frame transmission/reception) Maximum 1 Mbps (during 16 MHz clock input) * Allocated to common access-enabled RAM area * RAM that is mapped to an unused message byte can be used for CPU processing or other processing Mask functions * Four * Global masks and local masks can be used without distinction Message configuration No. of messages Message storage method Can be declared as transmit message or receive message 32 messages * Storage in receive buffer corresponding to each ID * Storage in buffer specified by receive mask function Remote reception * Remote frames can be received in either the receive message buffer or the transmit message buffer * If a remote frame is received by a transmit message buffer, there is a choice between having the remote request processed by the CPU or starting the auto transmit function. Remote transmission The remote frame can be sent either by setting the transmit message's RTR bit (M_CTRLn register) or by setting the receive message's send request. Time stamp function Diagnostic functions A time stamp function can be set for receive messages and transmit messages. * Read-enabled error counter provided. * "Valid protocol operation flag" provided for verification of bus connections. * Receive-only mode (with auto baud rate detection) provided. * Diagnostic processing mode provided. Low-power mode * CAN sleep mode (wakeup function using CAN bus enabled) * CAN stop mode (wakeup function using CAN bus disabled) Remark n = 00 to 31 User's Manual U14665EJ4V0UD 405 CHAPTER 18 FCAN CONTROLLER 18.2 Configuration FCAN is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC Electronics peripheral I/O bus) interface as a means of transmitting and receiving signals. (2) MAC (Memory Access Controller) This functional block controls access to the CAN module within the FCAN and to the CAN RAM. (3) CAN module This functional block is involved in the operation of the CAN protocol layer and its related settings. (4) CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. 406 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-1. Block Diagram of FCAN CPU Interrupt request INTCEn INTCRn INTCTn INTCME NPB (NEC Peripheral I/O Bus) FCAN controller CANTX1 NPB interface MAC (Memory Access Controller) CAN module 1 CAN module 2 CANRX1 CANTX2Note CANRX2Note CAN transceiver 1 CAN transceiver 2 CAN_L CAN_H CAN_L CAN bus CAN_H CAN RAM Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 31 C1MASK0 C1MASK1 C1MASK2 C1MASK3 C2MASK0 C2MASK1 C2MASK2 C2MASK3 Note PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y only Cautions 1. When P114/CANTX1, P115/CANRX1, P116/CANTX2, P117/CANRX2 are used during FCAN transmission/reception, they can be used as FCAN pin functions (CANTX1, CANRX1, CANTX2, CANRX2) by setting the port alternate-function control register (PAC) (refer to 5.2.10 (2) (b) Port alternate-function control register (PAC)). 2. When the P114/CANTX1 and P116/CANTX2 pins are used as CANTX1, CANTX2, set both the P11 and PM11 registers to 0 (refer to 5.3 Setting When Port Pin Is Used for Alternate Function). 3. When the P115/CANRX1 and P117/CANRX2 pins are used as CANRX1 and CANRX2, set the P11 register to 0 and the PM11 register to 1. 4. If an FCAN register is read/written when the external bus interface function is used, an address/data control signal is output to the external expansion pins (ports 4, 5, 6, 9), so read/write of xxmFF800H to xxmFFFFFH (m = 3, 7, B), which is the FCAN address area, should not be performed for the external devices connected to the external expansion pins. 5. If the wait function and idle function are set when the external bus interface function is used, these functions are enabled even when reading/writing the FCAN register. 6. Since no clock is supplied from the subclock to FCAN, when stopping the main clock and setting the subclock operation, do not read/write an FCAN register. Remark n = 1, 2 User's Manual U14665EJ4V0UD ... 407 CHAPTER 18 FCAN CONTROLLER 18.3 Internal Registers of FCAN Controller 18.3.1 Configuration of message buffers Table 18-2. Configuration of Message Buffers Address xxnFF800H to xxnFF81FH xxnFF820H to xxnFF83FH xxnFF840H to xxnFF85FH xxnFF860H to xxnFF87FH xxnFF880H to xxnFF89FH xxnFF8A0H to xxnFF8BFH xxnFF8C0H to xxnFF8DFH xxnFF8E0H to xxnFF8FFH xxnFF900H to xxnFF91FH xxnFF920H to xxnFF93FH xxnFF940H to xxnFF95FH xxnFF960H to xxnFF97FH xxnFF980H to xxnFF99FH xxnFF9A0H to xxnFF9BFH xxnFF9C0H to xxnFF9DFH xxnFF9E0H to xxnFF9FFH xxnFFA00H to xxnFFA1FH xxnFFA20H to xxnFFA3FH xxnFFA40H to xxnFFA5FH xxnFFA60H to xxnFFA7FH xxnFFA80H to xxnFFA9FH xxnFFAA0H to xxnFFABFH xxnFFAC0H to xxnFFADFH xxnFFAE0H to xxnFFAFFH xxnFFB00H to xxnFFB1FH xxnFFB20H to xxnFFB3FH xxnFFB40H to xxnFFB5FH xxnFFB60H to xxnFFB7FH xxnFFB80H to xxnFFB9FH xxnFFBA0H to xxnFFBBFH xxnFFBC0H to xxnFFBDFH xxnFFBE0H to xxnFFBFFH Register Name Message buffer 0 field Message buffer 1 field Message buffer 2 field Message buffer 3 field Message buffer 4 field Message buffer 5 field Message buffer 6 field Message buffer 7 field Message buffer 8 field Message buffer 9 field Message buffer 10 field Message buffer 11 field Message buffer 12 field Message buffer 13 field Message buffer 14 field Message buffer 15 field Message buffer 16 field Message buffer 17 field Message buffer 18 field Message buffer 19 field Message buffer 20 field Message buffer 21 field Message buffer 22 field Message buffer 23 field Message buffer 24 field Message buffer 25 field Message buffer 26 field Message buffer 27 field Message buffer 28 field Message buffer 29 field Message buffer 30 field Message buffer 31 field Remarks 1. For details of message buffers, see 18.3.2 List of FCAN registers. 2. n = 3, 7, B 408 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.3.2 List of FCAN registers (1/14) Bit Units for Manipulation 1 Bit 8 16 32 Bits Bits Bits R W R/W R W R/W 0000H Undefined 0000H Undefined Undefined Address Function Register Name Symbol R/W After Reset xxnFF804H xxnFF805H xxnFF806H xxnFF808H xxnFF809H xxnFF80AH xxnFF80BH xxnFF80CH xxnFF80DH xxnFF80EH xxnFF80FH xxnFF810H xxnFF812H xxnFF814H xxnFF815H xxnFF816H xxnFF824H xxnFF825H xxnFF826H xxnFF828H xxnFF829H xxnFF82AH xxnFF82BH xxnFF82CH xxnFF82DH xxnFF82EH xxnFF82FH xxnFF830H xxnFF832H xxnFF834H xxnFF835H xxnFF836H xxnFF844H xxnFF845H xxnFF846H xxnFF848H xxnFF849H xxnFF84AH xxnFF84BH xxnFF84CH CAN message data length register 00 CAN message control register 00 CAN message time stamp register 00 CAN message data register 000 CAN message data register 001 CAN message data register 002 CAN message data register 003 CAN message data register 004 CAN message data register 005 CAN message data register 006 CAN message data register 007 CAN message ID register L00 CAN message ID register H00 CAN message configuration register 00 CAN message status register 00 CAN status set/clear register 00 CAN message data length register 01 CAN message control register 01 CAN message time stamp register 01 CAN message data register 010 CAN message data register 011 CAN message data register 012 CAN message data register 013 CAN message data register 014 CAN message data register 015 CAN message data register 016 CAN message data register 017 CAN message ID register L01 CAN message ID register H01 CAN message configuration register 01 CAN message status register 01 CAN status set/clear register 01 CAN message data length register 02 CAN message control register 02 CAN message time stamp register 02 CAN message data register 020 CAN message data register 021 CAN message data register 022 CAN message data register 023 CAN message data register 024 M_DLC00 M_CTRL00 M_TIME00 M_DATA000 M_DATA001 M_DATA002 M_DATA003 M_DATA004 M_DATA005 M_DATA006 M_DATA007 M_IDL00 M_IDH00 M_CONF00 M_STAT00 SC_STAT00 M_DLC01 M_CTRL01 M_TIME01 M_DATA010 M_DATA011 M_DATA012 M_DATA013 M_DATA014 M_DATA015 M_DATA016 M_DATA017 M_IDL01 M_IDH01 M_CONF01 M_STAT01 SC_STAT01 M_DLC02 M_CTRL02 M_TIME02 M_DATA020 M_DATA021 M_DATA022 M_DATA023 M_DATA024 R/W Remark n = 3, 7, B User's Manual U14665EJ4V0UD 409 CHAPTER 18 FCAN CONTROLLER (2/14) Bit Units for Manipulation 1 Bit xxnFF84DH xxnFF84EH xxnFF84FH xxnFF850H xxnFF852H xxnFF854H xxnFF855H xxnFF856H xxnFF864H xxnFF865H xxnFF866H xxnFF868H xxnFF869H xxnFF86AH xxnFF86BH xxnFF86CH xxnFF86DH xxnFF86EH xxnFF86FH xxnFF870H xxnFF872H xxnFF874H xxnFF875H xxnFF876H xxnFF884H xxnFF885H xxnFF886H xxnFF888H xxnFF889H xxnFF88AH xxnFF88BH xxnFF88CH xxnFF88DH xxnFF88EH xxnFF88FH xxnFF890H xxnFF892H xxnFF894H xxnFF895H xxnFF896H xxnFF8A4H xxnFF8A5H CAN message data register 025 CAN message data register 026 CAN message data register 027 CAN message ID register L02 CAN message ID register H02 CAN message configuration register 02 CAN message status register 02 CAN status set/clear register 02 CAN message data length register 03 CAN message control register 03 CAN message time stamp register 03 CAN message data register 030 CAN message data register 031 CAN message data register 032 CAN message data register 033 CAN message data register 034 CAN message data register 035 CAN message data register 036 CAN message data register 037 CAN message ID register L03 CAN message ID register H03 CAN message configuration register 03 CAN message status register 03 CAN status set/clear register 03 CAN message data length register 04 CAN message control register 04 CAN message time stamp register 04 CAN message data register 040 CAN message data register 041 CAN message data register 042 CAN message data register 043 CAN message data register 044 CAN message data register 045 CAN message data register 046 CAN message data register 047 CAN message ID register L04 CAN message ID register H04 CAN message configuration register 04 CAN message status register 04 CAN status set/clear register 04 CAN message data length register 05 CAN message control register 05 M_DATA025 M_DATA026 M_DATA027 M_IDL02 M_IDH02 M_CONF02 M_STAT02 SC_STAT02 M_DLC03 M_CTRL03 M_TIME03 M_DATA030 M_DATA031 M_DATA032 M_DATA033 M_DATA034 M_DATA035 M_DATA036 M_DATA037 M_IDL03 M_IDH03 M_CONF03 M_STAT03 SC_STAT03 M_DLC04 M_CTRL04 M_TIME04 M_DATA040 M_DATA041 M_DATA042 M_DATA043 M_DATA044 M_DATA045 M_DATA046 M_DATA047 M_IDL04 M_IDH04 M_CONF04 M_STAT04 SC_STAT04 M_DLC05 M_CTRL05 R W R/W 0000H Undefined R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B 410 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (3/14) Bit Units for Manipulation 1 Bit xxnFF8A6H xxnFF8A8H xxnFF8A9H xxnFF8AAH xxnFF8ABH xxnFF8ACH xxnFF8ADH xxnFF8AEH xxnFF8AFH xxnFF8B0H xxnFF8B2H xxnFF8B4H xxnFF8B5H xxnFF8B6H xxnFF8C4H xxnFF8C5H xxnFF8C6H xxnFF8C8H xxnFF8C9H xxnFF8CAH xxnFF8CBH xxnFF8CCH xxnFF8CDH xxnFF8CEH xxnFF8CFH xxnFF8D0H xxnFF8D2H xxnFF8D4H xxnFF8D5H xxnFF8D6H xxnFF8E4H xxnFF8E5H xxnFF8E6H xxnFF8E8H xxnFF8E9H xxnFF8EAH xxnFF8EBH xxnFF8ECH xxnFF8EDH xxnFF8EEH xxnFF8EFH xxnFF8F0H xxnFF8F2H CAN message time stamp register 05 CAN message data register 050 CAN message data register 051 CAN message data register 052 CAN message data register 053 CAN message data register 054 CAN message data register 055 CAN message data register 056 CAN message data register 057 CAN message ID register L05 CAN message ID register H05 CAN message configuration register 05 CAN message status register 05 CAN status set/clear register 05 CAN message data length register 06 CAN message control register 06 CAN message time stamp register 06 CAN message data register 060 CAN message data register 061 CAN message data register 062 CAN message data register 063 CAN message data register 064 CAN message data register 065 CAN message data register 066 CAN message data register 067 CAN message ID register L06 CAN message ID register H06 CAN message configuration register 06 CAN message status register 06 CAN status set/clear register 06 CAN message data length register 07 CAN message control register 07 CAN message time stamp register 07 CAN message data register 070 CAN message data register 071 CAN message data register 072 CAN message data register 073 CAN message data register 074 CAN message data register 075 CAN message data register 076 CAN message data register 077 CAN message ID register L07 CAN message ID register H07 M_TIME05 M_DATA050 M_DATA051 M_DATA052 M_DATA053 M_DATA054 M_DATA055 M_DATA056 M_DATA057 M_IDL05 M_IDH05 M_CONF05 M_STAT05 SC_STAT05 M_DLC06 M_CTRL06 M_TIME06 M_DATA060 M_DATA061 M_DATA062 M_DATA063 M_DATA064 M_DATA065 M_DATA066 M_DATA067 M_IDL06 M_IDH06 M_CONF06 M_STAT06 SC_STAT06 M_DLC07 M_CTRL07 M_TIME07 M_DATA070 M_DATA071 M_DATA072 M_DATA073 M_DATA074 M_DATA075 M_DATA076 M_DATA077 M_IDL07 M_IDH07 R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 411 CHAPTER 18 FCAN CONTROLLER (4/14) Bit Units for Manipulation 1 Bit xxnFF8F4H xxnFF8F5H xxnFF8F6H xxnFF904H xxnFF905H xxnFF906H xxnFF908H xxnFF909H xxnFF90AH xxnFF90BH xxnFF90CH xxnFF90DH xxnFF90EH xxnFF90FH xxnFF910H xxnFF912H xxnFF914H xxnFF915H xxnFF916H xxnFF924H xxnFF925H xxnFF926H xxnFF928H xxnFF929H xxnFF92AH xxnFF92BH xxnFF92CH xxnFF92DH xxnFF92EH xxnFF92FH xxnFF930H xxnFF932H xxnFF934H xxnFF935H xxnFF936H xxnFF944H xxnFF945H xxnFF946H xxnFF948H xxnFF949H xxnFF94AH xxnFF94BH CAN message configuration register 07 CAN message status register 07 CAN status set/clear register 07 CAN message data length register 08 CAN message control register 08 CAN message time stamp register 08 CAN message data register 080 CAN message data register 081 CAN message data register 082 CAN message data register 083 CAN message data register 084 CAN message data register 085 CAN message data register 086 CAN message data register 087 CAN message ID register L08 CAN message ID register H08 CAN message configuration register 08 CAN message status register 08 CAN status set/clear register 08 CAN message data length register 09 CAN message control register 09 CAN message time stamp register 09 CAN message data register 090 CAN message data register 091 CAN message data register 092 CAN message data register 093 CAN message data register 094 CAN message data register 095 CAN message data register 096 CAN message data register 097 CAN message ID register L09 CAN message ID register H09 CAN message configuration register 09 CAN message status register 09 CAN status set/clear register 09 CAN message data length register 10 CAN message control register 10 CAN message time stamp register 10 CAN message data register 100 CAN message data register 101 CAN message data register 102 CAN message data register 103 M_CONF07 M_STAT07 SC_STAT07 M_DLC08 M_CTRL08 M_TIME08 M_DATA080 M_DATA081 M_DATA082 M_DATA083 M_DATA084 M_DATA085 M_DATA086 M_DATA087 M_IDL08 M_IDH08 M_CONF08 M_STAT08 SC_STAT08 M_DLC09 M_CTRL09 M_TIME09 M_DATA090 M_DATA091 M_DATA092 M_DATA093 M_DATA094 M_DATA095 M_DATA096 M_DATA097 M_IDL09 M_IDH09 M_CONF09 M_STAT09 SC_STAT09 M_DLC10 M_CTRL10 M_TIME10 M_DATA100 M_DATA101 M_DATA102 M_DATA103 R W R/W 0000H Undefined R W R/W 0000H Undefined R/W R W R/W 8 16 32 Bits Bits Bits 0000H Undefined Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B 412 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (5/14) Bit Units for Manipulation 1 Bit xxnFF94CH xxnFF94DH xxnFF94EH xxnFF94FH xxnFF950H xxnFF952H xxnFF954H xxnFF955H xxnFF956H xxnFF964H xxnFF965H xxnFF966H xxnFF968H xxnFF969H xxnFF96AH xxnFF96BH xxnFF96CH xxnFF96DH xxnFF96EH xxnFF96FH xxnFF970H xxnFF972H xxnFF974H xxnFF975H xxnFF976H xxnFF984H xxnFF985H xxnFF986H xxnFF988H xxnFF989H xxnFF98AH xxnFF98BH xxnFF98CH xxnFF98DH xxnFF98EH xxnFF98FH xxnFF990H xxnFF992H xxnFF994H xxnFF995H xxnFF996H xxnFF9A4H CAN message data register 104 CAN message data register 105 CAN message data register 106 CAN message data register 107 CAN message ID register L10 CAN message ID register H10 CAN message configuration register 10 CAN message status register 10 CAN status set/clear register 10 CAN message data length register 11 CAN message control register 11 CAN message time stamp register 11 CAN message data register 110 CAN message data register 111 CAN message data register 112 CAN message data register 113 CAN message data register 114 CAN message data register 115 CAN message data register 116 CAN message data register 117 CAN message ID register L11 CAN message ID register H11 CAN message configuration register 11 CAN message status register 11 CAN status set/clear register 11 CAN message data length register 12 CAN message control register 12 CAN message time stamp register 12 CAN message data register 120 CAN message data register 121 CAN message data register 122 CAN message data register 123 CAN message data register 124 CAN message data register 125 CAN message data register 126 CAN message data register 127 CAN message ID register L12 CAN message ID register H12 CAN message configuration register 12 CAN message status register 12 CAN status set/clear register 12 CAN message data length register 13 M_DATA104 M_DATA105 M_DATA106 M_DATA107 M_IDL10 M_IDH10 M_CONF10 M_STAT10 SC_STAT10 M_DLC11 M_CTRL11 M_TIME11 M_DATA110 M_DATA111 M_DATA112 M_DATA113 M_DATA114 M_DATA115 M_DATA116 M_DATA117 M_IDL11 M_IDH11 M_CONF11 M_STAT11 SC_STAT11 M_DLC12 M_CTRL12 M_TIME12 M_DATA120 M_DATA121 M_DATA122 M_DATA123 M_DATA124 M_DATA125 M_DATA126 M_DATA127 M_IDL12 M_IDH12 M_CONF12 M_STAT12 SC_STAT12 M_DLC13 R W R/W 0000H Undefined R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 413 CHAPTER 18 FCAN CONTROLLER (6/14) Bit Units for Manipulation 1 Bit xxnFF9A5H xxnFF9A6H xxnFF9A8H xxnFF9A9H xxnFF9AAH xxnFF9ABH xxnFF9ACH xxnFF9ADH xxnFF9AEH xxnFF9AFH xxnFF9B0H xxnFF9B2H xxnFF9B4H xxnFF9B5H xxnFF9B6H xxnFF9C4H xxnFF9C5H xxnFF9C6H xxnFF9C8H xxnFF9C9H xxnFF9CAH xxnFF9CBH xxnFF9CCH xxnFF9CDH xxnFF9CEH xxnFF9CFH xxnFF9D0H xxnFF9D2H xxnFF9D4H xxnFF9D5H xxnFF9D6H xxnFF9E4H xxnFF9E5H xxnFF9E6H xxnFF9E8H xxnFF9E9H xxnFF9EAH xxnFF9EBH xxnFF9ECH xxnFF9EDH xxnFF9EEH xxnFF9EFH CAN message control register 13 CAN message time stamp register 13 CAN message data register 130 CAN message data register 131 CAN message data register 132 CAN message data register 133 CAN message data register 134 CAN message data register 135 CAN message data register 136 CAN message data register 137 CAN message ID register L13 CAN message ID register H13 CAN message configuration register 13 CAN message status register 13 CAN status set/clear register 13 CAN message data length register 14 CAN message control register 14 CAN message time stamp register 14 CAN message data register 140 CAN message data register 141 CAN message data register 142 CAN message data register 143 CAN message data register 144 CAN message data register 145 CAN message data register 146 CAN message data register 147 CAN message ID register L14 CAN message ID register H14 CAN message configuration register 14 CAN message status register 14 CAN status set/clear register 14 CAN message data length register 15 CAN message control register 15 CAN message time stamp register 15 CAN message data register 150 CAN message data register 151 CAN message data register 152 CAN message data register 153 CAN message data register 154 CAN message data register 155 CAN message data register 156 CAN message data register 157 M_CTRL13 M_TIME13 M_DATA130 M_DATA131 M_DATA132 M_DATA133 M_DATA134 M_DATA135 M_DATA136 M_DATA137 M_IDL13 M_IDH13 M_CONF13 M_STAT13 SC_STAT13 M_DLC14 M_CTRL14 M_TIME14 M_DATA140 M_DATA141 M_DATA142 M_DATA143 M_DATA144 M_DATA145 M_DATA146 M_DATA147 M_IDL14 M_IDH14 M_CONF14 M_STAT14 SC_STAT14 M_DLC15 M_CTRL15 M_TIME15 M_DATA150 M_DATA151 M_DATA152 M_DATA153 M_DATA154 M_DATA155 M_DATA156 M_DATA157 R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B 414 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (7/14) Bit Units for Manipulation 1 Bit xxnFF9F0H xxnFF9F2H xxnFF9F4H xxnFF9F5H xxnFF9F6H xxnFFA04H xxnFFA05H xxnFFA06H xxnFFA08H xxnFFA09H xxnFFA0AH xxnFFA0BH xxnFFA0CH xxnFFA0DH xxnFFA0EH xxnFFA0FH xxnFFA10H xxnFFA12H xxnFFA14H xxnFFA15H xxnFFA16H xxnFFA24H xxnFFA25H xxnFFA26H xxnFFA28H xxnFFA29H xxnFFA2AH xxnFFA2BH xxnFFA2CH xxnFFA2DH xxnFFA2EH xxnFFA2FH xxnFFA30H xxnFFA32H xxnFFA34H xxnFFA35H xxnFFA36H xxnFFA44H xxnFFA45H xxnFFA46H xxnFFA48H xxnFFA49H CAN message ID register L15 CAN message ID register H15 CAN message configuration register 15 CAN message status register 15 CAN status set/clear register 15 CAN message data length register 16 CAN message control register 16 CAN message time stamp register 16 CAN message data register 160 CAN message data register 161 CAN message data register 162 CAN message data register 163 CAN message data register 164 CAN message data register 165 CAN message data register 166 CAN message data register 167 CAN message ID register L16 CAN message ID register H16 CAN message configuration register 16 CAN message status register 16 CAN status set/clear register 16 CAN message data length register 17 CAN message control register 17 CAN message time stamp register 17 CAN message data register 170 CAN message data register 171 CAN message data register 172 CAN message data register 173 CAN message data register 174 CAN message data register 175 CAN message data register 176 CAN message data register 177 CAN message ID register L17 CAN message ID register H17 CAN message configuration register 17 CAN message status register 17 CAN status set/clear register 17 CAN message data length register 18 CAN message control register 18 CAN message time stamp register 18 CAN message data register 180 CAN message data register 181 M_IDL15 M_IDH15 M_CONF15 M_STAT15 SC_STAT15 M_DLC16 M_CTRL16 M_TIME16 M_DATA160 M_DATA161 M_DATA162 M_DATA163 M_DATA164 M_DATA165 M_DATA166 M_DATA167 M_IDL16 M_IDH16 M_CONF16 M_STAT16 SC_STAT16 M_DLC17 M_CTRL17 M_TIME17 M_DATA170 M_DATA171 M_DATA172 M_DATA173 M_DATA174 M_DATA175 M_DATA176 M_DATA177 M_IDL17 M_IDH17 M_CONF17 M_STAT17 SC_STAT17 M_DLC18 M_CTRL18 M_TIME18 M_DATA180 M_DATA181 R W R/W 0000H Undefined R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 415 CHAPTER 18 FCAN CONTROLLER (8/14) Bit Units for Manipulation 1 Bit xxnFFA4AH xxnFFA4BH xxnFFA4CH xxnFFA4DH xxnFFA4EH xxnFFA4FH xxnFFA50H xxnFFA52H xxnFFA54H xxnFFA55H xxnFFA56H xxnFFA64H xxnFFA65H xxnFFA66H xxnFFA68H xxnFFA69H xxnFFA6AH xxnFFA6BH xxnFFA6CH xxnFFA6DH xxnFFA6EH xxnFFA6FH xxnFFA70H xxnFFA72H xxnFFA74H xxnFFA75H xxnFFA76H xxnFFA84H xxnFFA85H xxnFFA86H xxnFFA88H xxnFFA89H xxnFFA8AH xxnFFA8BH xxnFFA8CH xxnFFA8DH xxnFFA8EH xxnFFA8FH xxnFFA90H xxnFFA92H xxnFFA94H xxnFFA95H CAN message data register 182 CAN message data register 183 CAN message data register 184 CAN message data register 185 CAN message data register 186 CAN message data register 187 CAN message ID register L18 CAN message ID register H18 CAN message configuration register 18 CAN message status register 18 CAN status set/clear register 18 CAN message data length register 19 CAN message control register 19 CAN message time stamp register 19 CAN message data register 190 CAN message data register 191 CAN message data register 192 CAN message data register 193 CAN message data register 194 CAN message data register 195 CAN message data register 196 CAN message data register 197 CAN message ID register L19 CAN message ID register H19 CAN message configuration register 19 CAN message status register 19 CAN status set/clear register 19 CAN message data length register 20 CAN message control register 20 CAN message time stamp register 20 CAN message data register 200 CAN message data register 201 CAN message data register 202 CAN message data register 203 CAN message data register 204 CAN message data register 205 CAN message data register 206 CAN message data register 207 CAN message ID register L20 CAN message ID register H20 CAN message configuration register 20 CAN message status register 20 M_DATA182 M_DATA183 M_DATA184 M_DATA185 M_DATA186 M_DATA187 M_IDL18 M_IDH18 M_CONF18 M_STAT18 SC_STAT18 M_DLC19 M_CTRL19 M_TIME19 M_DATA190 M_DATA191 M_DATA192 M_DATA193 M_DATA194 M_DATA195 M_DATA196 M_DATA197 M_IDL19 M_IDH19 M_CONF19 M_STAT19 SC_STAT19 M_DLC20 M_CTRL20 M_TIME20 M_DATA200 M_DATA201 M_DATA202 M_DATA203 M_DATA204 M_DATA205 M_DATA206 M_DATA207 M_IDL20 M_IDH20 M_CONF20 M_STAT20 R R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B 416 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (9/14) Bit Units for Manipulation 1 Bit xxnFFA96H xxnFFAA4H xxnFFAA5H xxnFFAA6H xxnFFAA8H xxnFFAA9H xxnFFAAAH xxnFFAABH xxnFFAACH xxnFFAADH xxnFFAAEH xxnFFAAFH xxnFFAB0H xxnFFAB2H xxnFFAB4H xxnFFAB5H xxnFFAB6H xxnFFAC4H xxnFFAC5H xxnFFAC6H xxnFFAC8H xxnFFAC9H xxnFFACAH xxnFFACBH xxnFFACCH xxnFFACDH xxnFFACEH xxnFFACFH xxnFFAD0H xxnFFAD2H xxnFFAD4H xxnFFAD5H xxnFFAD6H xxnFFAE4H xxnFFAE5H xxnFFAE6H xxnFFAE8H xxnFFAE9H xxnFFAEAH xxnFFAEBH xxnFFAECH xxnFFAEDH CAN status set/clear register 20 CAN message data length register 21 CAN message control register 21 CAN message time stamp register 21 CAN message data register 210 CAN message data register 211 CAN message data register 212 CAN message data register 213 CAN message data register 214 CAN message data register 215 CAN message data register 216 CAN message data register 217 CAN message ID register L21 CAN message ID register H21 CAN message configuration register 21 CAN message status register 21 CAN status set/clear register 21 CAN message data length register 22 CAN message control register 22 CAN message time stamp register 22 CAN message data register 220 CAN message data register 221 CAN message data register 222 CAN message data register 223 CAN message data register 224 CAN message data register 225 CAN message data register 226 CAN message data register 227 CAN message ID register L22 CAN message ID register H22 CAN message configuration register 22 CAN message status register 22 CAN status set/clear register 22 CAN message data length register 23 CAN message control register 23 CAN message time stamp register 23 CAN message data register 230 CAN message data register 231 CAN message data register 232 CAN message data register 233 CAN message data register 234 CAN message data register 235 SC_STAT20 M_DLC21 M_CTRL21 M_TIME21 M_DATA210 M_DATA211 M_DATA212 M_DATA213 M_DATA214 M_DATA215 M_DATA216 M_DATA217 M_IDL21 M_IDH21 M_CONF21 M_STAT21 SC_STAT21 M_DLC22 M_CTRL22 M_TIME22 M_DATA220 M_DATA221 M_DATA222 M_DATA223 M_DATA224 M_DATA225 M_DATA226 M_DATA227 M_IDL22 M_IDH22 M_CONF22 M_STAT22 SC_STAT22 M_DLC23 M_CTRL23 M_TIME23 M_DATA230 M_DATA231 M_DATA232 M_DATA233 M_DATA234 M_DATA235 R W R/W 0000H Undefined R W R/W 0000H Undefined W R/W 8 16 32 Bits Bits Bits 0000H Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 417 CHAPTER 18 FCAN CONTROLLER (10/14) Bit Units for Manipulation 1 Bit xxnFFAEEH xxnFFAEFH xxnFFAF0H xxnFFAF2H xxnFFAF4H xxnFFAF5H xxnFFAF6H xxnFFB04H xxnFFB05H xxnFFB06H xxnFFB08H xxnFFB09H xxnFFB0AH xxnFFB0BH xxnFFB0CH xxnFFB0DH xxnFFB0EH xxnFFB0FH xxnFFB10H xxnFFB12H xxnFFB14H xxnFFB15H xxnFFB16H xxnFFB24H xxnFFB25H xxnFFB26H xxnFFB28H xxnFFB29H xxnFFB2AH xxnFFB2BH xxnFFB2CH xxnFFB2DH xxnFFB2EH xxnFFB2FH xxnFFB30H xxnFFB32H xxnFFB34H xxnFFB35H xxnFFB36H xxnFFB44H xxnFFB45H xxnFFB46H xxnFFB48H CAN message data register 236 CAN message data register 237 CAN message ID register L23 CAN message ID register H23 CAN message configuration register 23 CAN message status register 23 CAN status set/clear register 23 CAN message data length register 24 CAN message control register 24 CAN message time stamp register 24 CAN message data register 240 CAN message data register 241 CAN message data register 242 CAN message data register 243 CAN message data register 244 CAN message data register 245 CAN message data register 246 CAN message data register 247 CAN message ID register L24 CAN message ID register H24 CAN message configuration register 24 CAN message status register 24 CAN status set/clear register 24 CAN message data length register 25 CAN message control register 25 CAN message time stamp register 25 CAN message data register 250 CAN message data register 251 CAN message data register 252 CAN message data register 253 CAN message data register 254 CAN message data register 255 CAN message data register 256 CAN message data register 257 CAN message ID register L25 CAN message ID register H25 CAN message configuration register 25 CAN message status register 25 CAN status set/clear register 25 CAN message data length register 26 CAN message control register 26 CAN message time stamp register 26 CAN message data register 260 M_DATA236 M_DATA237 M_IDL23 M_IDH23 M_CONF23 M_STAT23 SC_STAT23 M_DLC24 M_CTRL24 M_TIME24 M_DATA240 M_DATA241 M_DATA242 M_DATA243 M_DATA244 M_DATA245 M_DATA246 M_DATA247 M_IDL24 M_IDH24 M_CONF24 M_STAT24 SC_STAT24 M_DLC25 M_CTRL25 M_TIME25 M_DATA250 M_DATA251 M_DATA252 M_DATA253 M_DATA254 M_DATA255 M_DATA256 M_DATA257 M_IDL25 M_IDH25 M_CONF25 M_STAT25 SC_STAT25 M_DLC26 M_CTRL26 M_TIME26 M_DATA260 R W R/W 0000H Undefined R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 418 CHAPTER 18 FCAN CONTROLLER (11/14) Bit Units for Manipulation 1 Bit xxnFFB49H xxnFFB4AH xxnFFB4BH xxnFFB4CH xxnFFB4DH xxnFFB4EH xxnFFB4FH xxnFFB50H xxnFFB52H xxnFFB54H xxnFFB55H xxnFFB56H xxnFFB64H xxnFFB65H xxnFFB66H xxnFFB68H xxnFFB69H xxnFFB6AH xxnFFB6BH xxnFFB6CH xxnFFB6DH xxnFFB6EH xxnFFB6FH xxnFFB70H xxnFFB72H xxnFFB74H xxnFFB75H xxnFFB76H xxnFFB84H xxnFFB85H xxnFFB86H xxnFFB88H xxnFFB89H xxnFFB8AH xxnFFB8BH xxnFFB8CH xxnFFB8DH xxnFFB8EH xxnFFB8FH xxnFFB90H xxnFFB92H xxnFFB94H CAN message data register 261 CAN message data register 262 CAN message data register 263 CAN message data register 264 CAN message data register 265 CAN message data register 266 CAN message data register 267 CAN message ID register L26 CAN message ID register H26 CAN message configuration register 26 CAN message status register 26 CAN status set/clear register 26 CAN message data length register 27 CAN message control register 27 CAN message time stamp register 27 CAN message data register 270 CAN message data register 271 CAN message data register 272 CAN message data register 273 CAN message data register 274 CAN message data register 275 CAN message data register 276 CAN message data register 277 CAN message ID register L27 CAN message ID register H27 CAN message configuration register 27 CAN message status register 27 CAN status set/clear register 27 CAN message data length register 28 CAN message control register 28 CAN message time stamp register 28 CAN message data register 280 CAN message data register 281 CAN message data register 282 CAN message data register 283 CAN message data register 284 CAN message data register 285 CAN message data register 286 CAN message data register 287 CAN message ID register L28 CAN message ID register H28 CAN message configuration register 28 M_DATA261 M_DATA262 M_DATA263 M_DATA264 M_DATA265 M_DATA266 M_DATA267 M_IDL26 M_IDH26 M_CONF26 M_STAT26 SC_STAT26 M_DLC27 M_CTRL27 M_TIME27 M_DATA270 M_DATA271 M_DATA272 M_DATA273 M_DATA274 M_DATA275 M_DATA276 M_DATA277 M_IDL27 M_IDH27 M_CONF27 M_STAT27 SC_STAT27 M_DLC28 M_CTRL28 M_TIME28 M_DATA280 M_DATA281 M_DATA282 M_DATA283 M_DATA284 M_DATA285 M_DATA286 M_DATA287 M_IDL28 M_IDH28 M_CONF28 R W R/W 0000H Undefined R W R/W 0000H Undefined R/W 8 16 32 Bits Bits Bits Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B User's Manual U14665EJ4V0UD 419 CHAPTER 18 FCAN CONTROLLER (12/14) Bit Units for Manipulation 1 Bit xxnFFB95H xxnFFB96H xxnFFBA4H xxnFFBA5H xxnFFBA6H xxnFFBA8H xxnFFBA9H xxnFFBAAH xxnFFBABH xxnFFBACH xxnFFBADH xxnFFBAEH xxnFFBAFH xxnFFBB0H xxnFFBB2H xxnFFBB4H xxnFFBB5H xxnFFBB6H xxnFFBC4H xxnFFBC5H xxnFFBC6H xxnFFBC8H xxnFFBC9H xxnFFBCAH xxnFFBCBH xxnFFBCCH xxnFFBCDH xxnFFBCEH xxnFFBCFH xxnFFBD0H xxnFFBD2H xxnFFBD4H xxnFFBD5H xxnFFBD6H xxnFFBE4H xxnFFBE5H xxnFFBE6H xxnFFBE8H xxnFFBE9H xxnFFBEAH xxnFFBEBH xxnFFBECH CAN message status register 28 CAN status set/clear register 28 CAN message data length register 29 CAN message control register 29 CAN message time stamp register 29 CAN message data register 290 CAN message data register 291 CAN message data register 292 CAN message data register 293 CAN message data register 294 CAN message data register 295 CAN message data register 296 CAN message data register 297 CAN message ID register L29 CAN message ID register H29 CAN message configuration register 29 CAN message status register 29 CAN status set/clear register 29 CAN message data length register 30 CAN message control register 30 CAN message time stamp register 30 CAN message data register 300 CAN message data register 301 CAN message data register 302 CAN message data register 303 CAN message data register 304 CAN message data register 305 CAN message data register 306 CAN message data register 307 CAN message ID register L30 CAN message ID register H30 CAN message configuration register 30 CAN message status register 30 CAN status set/clear register 30 CAN message data length register 31 CAN message control register 31 CAN message time stamp register 31 CAN message data register 310 CAN message data register 311 CAN message data register 312 CAN message data register 313 CAN message data register 314 M_STAT28 SC_STAT28 M_DLC29 M_CTRL29 M_TIME29 M_DATA290 M_DATA291 M_DATA292 M_DATA293 M_DATA294 M_DATA295 M_DATA296 M_DATA297 M_IDL29 M_IDH29 M_CONF29 M_STAT29 SC_STAT29 M_DLC30 M_CTRL30 M_TIME30 M_DATA300 M_DATA301 M_DATA302 M_DATA303 M_DATA304 M_DATA305 M_DATA306 M_DATA307 M_IDL30 M_IDH30 M_CONF30 M_STAT30 SC_STAT30 M_DLC31 M_CTRL31 M_TIME31 M_DATA310 M_DATA311 M_DATA312 M_DATA313 M_DATA314 R W R/W 0000H Undefined R W R/W 0000H Undefined R W R/W 8 16 32 Bits Bits Bits Undefined 0000H Undefined Address Function Register Name Symbol R/W After Reset Remark n = 3, 7, B 420 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (13/14) Bit Units for Manipulation 1 Bit xxnFFBEDH xxnFFBEEH xxnFFBEFH xxnFFBF0H xxnFFBF2H xxnFFBF4H xxnFFBF5H xxnFFBF6H xxnFFC00H xxnFFC02H xxnFFC04H xxnFFC06H xxnFFC0CH xxnFFC10H xxnFFC12H xxnFFC14H xxnFFC18H xxnFFC1AH CAN message data register 315 CAN message data register 316 CAN message data register 317 CAN message ID register L31 CAN message ID register H31 CAN message configuration register 31 CAN message status register 31 CAN status set/clear register 31 CAN interrupt pending register CAN global interrupt pending register CAN1 interrupt pending register CAN2 interrupt pending register CAN stop register CAN global status register CAN global interrupt enable register CAN main clock selection register CAN time stamp count register CAN message search start register CAN message search result register xxnFFC40H xxnFFC42H xxnFFC44H xxnFFC46H xxnFFC48H xxnFFC4AH xxnFFC4CH xxnFFC4EH xxnFFC50H xxnFFC52H xxnFFC54H xxnFFC56H xxnFFC58H xxnFFC5AH xxnFFC5CH CAN1 address mask 0 register L CAN1 address mask 0 register H CAN1 address mask 1 register L CAN1 address mask 1 register H CAN1 address mask 2 register L CAN1 address mask 2 register H CAN1 address mask 3 register L CAN1 address mask 3 register H CAN1 control register CAN1 definition register CAN1 information register CAN1 error count register CAN1 interrupt enable register CAN1 bus active register CAN1 bit rate prescaler register CAN1 bus diagnostic information register xxnFFC5EH xxnFFC80H xxnFFC82H xxnFFC84H xxnFFC86H xxnFFC88H CAN1 synchronization control register CAN2 address mask 0 register L Note Note Note Address Function Register Name Symbol R/W After Reset 8 16 32 Bits Bits Bits Undefined M_DATA315 M_DATA316 M_DATA317 M_IDL31 M_IDH31 M_CONF31 M_STAT31 SC_STAT31 CCINTP CGINTP C1INTP C2INTP CSTOP CGST CGIE CGCS CGTSC CGMSS CGMSR C1MASKL0 C1MASKH0 C1MASKL1 C1MASKH1 C1MASKL2 C1MASKH2 C1MASKL3 C1MASKH3 C1CTRL C1DEF C1LAST C1ERC C1IE C1BA C1BRP C1DINF C1SYNC C2MASKL0 C2MASKH0 C2MASKL1 C2MASKH1 C2MASKL2 R/W R W R R/W 0100H 0A00H 7F05H 0000H 0000H R W R R/W Undefined 0101H 0000H 00FFH 0000H 0900H 00FFH 0000H R R/W R R/W R R/W 0218H Undefined CAN2 address mask 0 register H CAN2 address mask 1 register L Note CAN2 address mask 1 register H CAN2 address mask 2 register L Note Note Note PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y only Remark n = 3, 7, B User's Manual U14665EJ4V0UD 421 CHAPTER 18 FCAN CONTROLLER (14/14) Bit Units for Address Function Register Name Symbol R/W 1 Bit xxnFFC8AH xxnFFC8CH xxnFFC8EH xxnFFC90H xxnFFC92H xxnFFC94H xxnFFC96H xxnFFC98H xxnFFC9AH xxnFFC9CH CAN2 address mask 2 register H CAN2 address mask 3 register L Note Manipulation 8 16 32 Bits Bits Bits After Reset C2MASKH2 C2MASKL3 C2MASKH3 C2CTRL C2DEF C2LAST C2ERC R/W Undefined Note CAN2 address mask 3 register H CAN2 control register Note Note 0101H 0000H 00FFH 0000H 0900H 00FFH 0000H CAN2 definition register Note CAN2 information register CAN2 error count register Note R Note CAN2 interrupt enable register CAN2 bus active register Note Note C2IE C2BA R/W R R/W R R/W CAN2 bit rate prescaler register Note C2BRP Note CAN2 bus diagnostic information register xxnFFC9EH CAN2 synchronization control register Note C2DINF C2SYNC 0218H Note PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y only Remark n = 3, 7, B 422 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4 Control Registers 18.4.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) The M_DLCn register sets the byte count in the data field of CAN message buffer n (n = 00 to 31). When receiving, the receive data field's byte count is set (1). These registers can be read/written in 8-bit units. Caution When the remote frame is received at the extended ID and is stored in the receive message buffer, the values of the DLC3 to DLC0 bits are cleared (0) regardless of the values of the DLC3 to DLC0 bits on the CAN bus. After reset: Undefined 7 M_DLCn (n = 00 to 31) DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 RFU Note R/W 6 RFU Note Address: See Table 18-3 4 Note 5 RFU 3 Note 2 DLC2 1 DLC1 0 DLC0 RFU DLC3 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data length code of transmit/receive message 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 8 bytes regardless of DLC3 to DLC0 values Other than above Note RFU (Reserved for Future Use) indicates a reserved bit. Be sure to set this bit to 0 when writing the M_DLCn register. User's Manual U14665EJ4V0UD 423 CHAPTER 18 FCAN CONTROLLER Table 18-3. Addresses of M_DLCn (n = 00 to 31) Register Name M_DLC00 M_DLC01 M_DLC02 M_DLC03 M_DLC04 M_DLC05 M_DLC06 M_DLC07 M_DLC08 M_DLC09 M_DLC10 M_DLC11 M_DLC12 M_DLC13 M_DLC14 M_DLC15 Address (m = 3, 7, B) xxmFF804H xxmFF824H xxmFF844H xxmFF864H xxmFF884H xxmFF8A4H xxmFF8C4H xxmFF8E4H xxmFF904H xxmFF924H xxmFF944H xxmFF964H xxmFF984H xxmFF9A4H xxmFF9C4H xxmFF9E4H Register Name M_DLC16 M_DLC17 M_DLC18 M_DLC19 M_DLC20 M_DLC21 M_DLC22 M_DLC23 M_DLC24 M_DLC25 M_DLC26 M_DLC27 M_DLC28 M_DLC29 M_DLC30 M_DLC31 Address (m = 3, 7, B) xxmFFA04H xxmFFA24H xxmFFA44H xxmFFA64H xxmFFA84H xxmFFAA4H xxmFFAC4H xxmFFAE4H xxmFFB04H xxmFFB24H xxmFFB44H xxmFFB64H xxmFFB84H xxmFFBA4H xxmFFBC4H xxmFFBE4H 424 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.2 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) The M_CTRLn register is used to set the frame format of the data field in messages stored in CAN message buffer n (n = 00 to 31). These registers can be read/written in 8-bit units. (1/2) After reset: Undefined 7 M_CTRLn (n = 00 to 31) RMDE1 Specifies operation of DN flag when remote frame is received by a transmit message buffer 0 1 DN flag not set when remote frame is received DN flag set when remote frame is received RMDE1 6 RMDE0 R/W 5 ATS Address: See Table 18-4 4 IE 3 MOVR 2 RFU Notes 1, 2 1 RFU Notes 1, 3 0 RTR * When the RMDE1 bit is set, the setting of the RMDE0 bit is irrelevant. * If a remote frame is received by the transmit message buffer when the RMDE1 bit has not been set, the CPU is not notified, nor are other operations performed. RMDE0 0 1 Specification of set/clear status of remote frame auto acknowledge function Remote frame auto acknowledge function cleared Remote frame auto acknowledge function set * The RMDE0 bit's setting is used only for transmit messages. * When the RTR bit has been set (1) (when the receive message or transmit message has a remote frame), the RMDE0 bit is processed as RMDE0 = 0. This prevents a worst-case scenario (in which transmission of a remote frame draws a 100% bus load due to reception of the same remote frame). ATS 0 1 Specifies whether or not to add a time stamp when transmitting Time stamp not added when transmitting Time stamp added when transmitting * The ATS bit is used only for transmit messages. * When the ATS bit has been set (1) and the data length code specifies at least two bytes, the last two bytes are replaced by a time stamp (see Table 18-12). The added time stamp counter value is sent to the bus via the message's SOF. When this occurs, the last two bytes (which are defined as a data field) are ignored. Notes 1. RFU (Reserved for Future Use) indicates a reserved bit. Be sure to set this bit to 0 when writing the M_DLCn register. 2. The value of the r1 bit on the CAN bus is set during reception. 3. The value of the r0 bit on the CAN bus is set during reception. Remark DN: Bit 2 of M_STATm (see 18.4.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)) User's Manual U14665EJ4V0UD 425 CHAPTER 18 FCAN CONTROLLER (2/2) IE 0 1 Specifies the enable/disable setting for interrupt requests Interrupt requests disabled Interrupt requests enabled * An interrupt request occurs when interrupts are enabled under the following conditions. * When a message is sent from the transmit message buffer * When a message is received by the receive message buffer * When a remote frame has been transmitted from the receive message buffer * When a remote frame is received by the transmit message buffer when the auto acknowledge function has not been set (RMDE0 bit = 0). * An interrupt request does not occur when an interrupt is enabled under the following conditions. * When a remote frame is received by the transmit message buffer when the auto acknowledge function has been set (RMDE0 bit = 1) * An interrupt request occurs even if the interrupt is disabled under the following conditions. * When a remote frame is received by the receive message buffer when the auto acknowledge function has not been set (RMDE0 bit = 0). MOVR 0 1 Message buffer overwrite Overwrite does not occur after DN bit is cleared Overwrite occurs at least once after DN bit is cleared * An overwrite of the message buffer occurs when the CAN module writes new data to the message buffer or when the DN bit has already been set (1). The MOVR bit is updated each time new data is stored in the message buffer. RTR 0 1 Specification of frame type Data frame transmit/receive Remote frame transmit/receive * When the RTR bit has been set (1) for a transmit message, a remote frame is transmitted instead of a data frame. Remark DN: Bit 2 of M_STATm (see 18.4.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)) 426 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Table 18-4. Addresses of M_CTRLn (n = 00 to 31) Register Name M_CTRL00 M_CTRL01 M_CTRL02 M_CTRL03 M_CTRL04 M_CTRL05 M_CTRL06 M_CTRL07 M_CTRL08 M_CTRL09 M_CTRL10 M_CTRL11 M_CTRL12 M_CTRL13 M_CTRL14 M_CTRL15 Address (m = 3, 7, B) xxmFF805H xxmFF825H xxmFF845H xxmFF865H xxmFF885H xxmFF8A5H xxmFF8C5H xxmFF8E5H xxmFF905H xxmFF925H xxmFF945H xxmFF965H xxmFF985H xxmFF9A5H xxmFF9C5H xxmFF9E5H Register Name M_CTRL16 M_CTRL17 M_CTRL18 M_CTRL19 M_CTRL20 M_CTRL21 M_CTRL22 M_CTRL23 M_CTRL24 M_CTRL25 M_CTRL26 M_CTRL27 M_CTRL28 M_CTRL29 M_CTRL30 M_CTRL31 Address (m = 3, 7, B) xxmFFA05H xxmFFA25H xxmFFA45H xxmFFA65H xxmFFA85H xxmFFAA5H xxmFFAC5H xxmFFAE5H xxmFFB05H xxmFFB25H xxmFFB45H xxmFFB65H xxmFFB85H xxmFFBA5H xxmFFBC5H xxmFFBE5H 18.4.3 CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) The M_TIMEn register is the register where the time stamp counter value is written upon completion of data reception (n = 00 to 31). These registers can be read/written in 16-bit units. After reset: Undefined R/W Address: see Table 18-5 M_TIMEn (n = 00 to 31) TS 15 TS 14 TS 13 TS 12 TS 11 TS 10 TS 09 TS 08 TS 07 TS 06 TS 05 TS 04 TS 03 TS 02 TS 01 TS 00 TS15 to TS0 These indicate the time stamp counter value. Caution If a new information is stored in the message buffer when a data frame or a remote frame has been received in the receive message buffer, a 16-bit time tag (time stamp counter value) is stored in the M_TIMEn register only when the MT2 to MT0 bits of the M_CONFn register are set to other than 000 or 110 (receive message). This time tag is specified by the time stamp setting, and is the time stamp counter value that is captured when the SOF is transmitted to the CAN bus or the value that is captured when data is written to the message buffer by the CAN module. User's Manual U14665EJ4V0UD 427 CHAPTER 18 FCAN CONTROLLER Table 18-5. Addresses of M_TIMEn (n = 00 to 31) Register Name M_TIME00 M_TIME01 M_TIME02 M_TIME03 M_TIME04 M_TIME05 M_TIME06 M_TIME07 M_TIME08 M_TIME09 M_TIME10 M_TIME11 M_TIME12 M_TIME13 M_TIME14 M_TIME15 Address (m = 3, 7, B) xxmFF806H xxmFF826H xxmFF846H xxmFF866H xxmFF886H xxmFF8A6H xxmFF8C6H xxmFF8E6H xxmFF906H xxmFF926H xxmFF946H xxmFF966H xxmFF986H xxmFF9A6H xxmFF9C6H xxmFF9E6H Register Name M_TIME16 M_TIME17 M_TIME18 M_TIME19 M_TIME20 M_TIME21 M_TIME22 M_TIME23 M_TIME24 M_TIME25 M_TIME26 M_TIME27 M_TIME28 M_TIME29 M_TIME30 M_TIME31 Address (m = 3, 7, B) xxmFFA06H xxmFFA26H xxmFFA46H xxmFFA66H xxmFFA86H xxmFFAA6H xxmFFAC6H xxmFFAE6H xxmFFB06H xxmFFB26H xxmFFB46H xxmFFB66H xxmFFB86H xxmFFBA6H xxmFFBC6H xxmFFBE6H 428 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.4 CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) The M_DATAn0 to M_DATAn7 registers are areas where up to 8 bytes of transmit or receive data is stored. These registers can be read/written in 8-bit units. Remark n = 00 to 31, x = 0 to 7 After reset: Undefined R/W Address: see Table 18-6 M_DATAn0 (n = 00 to 31) M_DATAn1 (n = 00 to 31) M_DATAn2 (n = 00 to 31) M_DATAn3 (n = 00 to 31) M_DATAn4 (n = 00 to 31) M_DATAn5 (n = 00 to 31) M_DATAn6 (n = 00 to 31) M_DATAn7 (n = 00 to 31) D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 D3_7 D3_6 D3_5 D3_4 D3_3 D3_2 D3_1 D3_0 D4_7 D4_6 D4_5 D4_4 D4_3 D4_2 D4_1 D4_0 D5_7 D5_6 D5_5 D5_4 D5_3 D5_2 D5_1 D5_0 D6_7 D6_6 D6_5 D6_4 D6_3 D6_2 D6_1 D6_0 D7_7 D7_6 D7_5 D7_4 D7_3 D7_2 D7_1 D7_0 M_DATAn0 These indicate the contents of the message data. to M_DATAn7 Cautions 1. The M_DATAn0 to M_DATAn7 registers are the fields (n = 00 to 31) that hold the receive and transmit data. When transmitting data, only the number of messages defined by the DLC3 to DLC0 bits of the M_DLCn register are transmitted to the CAN bus. 2. When the ATS bit of the M_CTRLn register is set (1) and the value of the DLC3 to DLC0 bits of the M_DLCn register is 2 bytes or higher, the last 2 bytes that are transmitted normally on the CAN bus are ignored and the time stamp value is transmitted. 3. When a new message is received, all the data fields are updated even if the value of the DLC3 to DLC0 bits of the M_DLCn register is lower than 8 bytes. The byte value of the data that is not received is invalid even if updated. User's Manual U14665EJ4V0UD 429 CHAPTER 18 FCAN CONTROLLER Table 18-6. Addresses of M_DATAnx (n = 00 to 31, x = 0 to 7) Register Name n M_DATAn0 (m = 3, 7, B) M_DATAn1 (m = 3, 7, B) xxmFF809H xxmFF829H xxmFF849H xxmFF869H xxmFF889H M_DATAn2 (m = 3, 7, B) xxmFF80AH xxmFF82AH xxmFF84AH xxmFF86AH xxmFF88AH M_DATAn3 (m = 3, 7, B) xxmFF80BH xxmFF82BH xxmFF84BH xxmFF86BH xxmFF88BH M_DATAn4 (m = 3, 7, B) M_DATAn5 (m = 3, 7, B) M_DATAn6 (m = 3, 7, B) xxmFF80EH xxmFF82EH xxmFF84EH xxmFF86EH xxmFF88EH M_DATAn7 (m = 3, 7, B) xxmFF80FH xxmFF82FH xxmFF84FH xxmFF86FH xxmFF88FH 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 xxmFF808H xxmFF828H xxmFF848H xxmFF868H xxmFF888H xxmFF8A8H xxmFF80CH xxmFF80DH xxmFF82CH xxmFF82DH xxmFF84CH xxmFF84DH xxmFF86CH xxmFF86DH xxmFF88CH xxmFF88DH xxmFF8A9H xxmFF8AAH xxmFF8ABH xxmFF8ACH xxmFF8ADH xxmFF8AEH xxmFF8AFH xxmFF8C8H xxmFF8C9H xxmFF8CAH xxmFF8CBH xxmFF8CCH xxmFF8CDH xxmFF8CEH xxmFF8CFH xxmFF8E8H xxmFF908H xxmFF928H xxmFF948H xxmFF968H xxmFF988H xxmFF9A8H xxmFF8E9H xxmFF8EAH xxmFF8EBH xxmFF8ECH xxmFF8EDH xxmFF8EEH xxmFF8EFH xxmFF909H xxmFF929H xxmFF949H xxmFF969H xxmFF989H xxmFF90AH xxmFF92AH xxmFF94AH xxmFF96AH xxmFF98AH xxmFF90BH xxmFF92BH xxmFF94BH xxmFF96BH xxmFF98BH xxmFF90CH xxmFF90DH xxmFF92CH xxmFF92DH xxmFF94CH xxmFF94DH xxmFF96CH xxmFF96DH xxmFF98CH xxmFF98DH xxmFF90EH xxmFF92EH xxmFF94EH xxmFF96EH xxmFF98EH xxmFF90FH xxmFF92FH xxmFF94FH xxmFF96FH xxmFF98FH xxmFF9A9H xxmFF9AAH xxmFF9ABH xxmFF9ACH xxmFF9ADH xxmFF9AEH xxmFF9AFH xxmFF9C8H xxmFF9C9H xxmFF9CAH xxmFF9CBH xxmFF9CCH xxmFF9CDH xxmFF9CEH xxmFF9CFH xxmFF9E8H xxmFFA08H xxmFFA28H xxmFFA48H xxmFFA68H xxmFFA88H xxmFF9E9H xxmFF9EAH xxmFF9EBH xxmFF9ECH xxmFF9EDH xxmFF9EEH xxmFF9EFH xxmFFA09H xxmFFA0AH xxmFFA0BH xxmFFA0CH xxmFFA0DH xxmFFA0EH xxmFFA0FH xxmFFA29H xxmFFA2AH xxmFFA2BH xxmFFA2CH xxmFFA2DH xxmFFA2EH xxmFFA2FH xxmFFA49H xxmFFA4AH xxmFFA4BH xxmFFA4CH xxmFFA4DH xxmFFA4EH xxmFFA4FH xxmFFA69H xxmFFA6AH xxmFFA6BH xxmFFA6CH xxmFFA6DH xxmFFA6EH xxmFFA6FH xxmFFA89H xxmFFA8AH xxmFFA8BH xxmFFA8CH xxmFFA8DH xxmFFA8EH xxmFFA8FH xxmFFAA8H xxmFFAA9H xxmFFAAAH xxmFFAABH xxmFFAACH xxmFFAADH xxmFFAAEH xxmFFAAFH xxmFFAC8H xxmFFAC9H xxmFFACAH xxmFFACBH xxmFFACCH xxmFFACDH xxmFFACEH xxmFFACFH xxmFFAE8H xxmFFAE9H xxmFFAEAH xxmFFAEBH xxmFFAECH xxmFFAEDH xxmFFAEEH xxmFFAEFH xxmFFB08H xxmFFB28H xxmFFB48H xxmFFB68H xxmFFB88H xxmFFB09H xxmFFB0AH xxmFFB0BH xxmFFB0CH xxmFFB0DH xxmFFB0EH xxmFFB0FH xxmFFB29H xxmFFB2AH xxmFFB2BH xxmFFB2CH xxmFFB2DH xxmFFB2EH xxmFFB2FH xxmFFB49H xxmFFB4AH xxmFFB4BH xxmFFB4CH xxmFFB4DH xxmFFB4EH xxmFFB4FH xxmFFB69H xxmFFB6AH xxmFFB6BH xxmFFB6CH xxmFFB6DH xxmFFB6EH xxmFFB6FH xxmFFB89H xxmFFB8AH xxmFFB8BH xxmFFB8CH xxmFFB8DH xxmFFB8EH xxmFFB8FH xxmFFBA8H xxmFFBA9H xxmFFBAAH xxmFFBABH xxmFFBACH xxmFFBADH xxmFFBAEH xxmFFBAFH xxmFFBC8H xxmFFBC9H xxmFFBCAH xxmFFBCBH xxmFFBCCH xxmFFBCDH xxmFFBCEH xxmFFBCFH xxmFFBE8H xxmFFBE9H xxmFFBEAH xxmFFBEBH xxmFFBECH xxmFFBEDH xxmFFBEEH xxmFFBEFH 430 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.5 CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) The M_IDLn and M_IDHn registers are areas used to set identifiers (n = 00 to 31). These registers can be read/written in 16-bit units. When in standard format mode, any data can be stored in the following areas. ID17 to ID10: First byte of receive dataNote is stored. ID9 to ID2: ID1, ID0: Second byte of receive dataNote is stored. Third byte (higher two bits) of receive dataNote is stored. Note See 18.4.4 CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7). After reset: Undefined 15 M_IDHn (n = 00 to 31) IDE 14 0 13 0 12 ID 28 R/W 11 ID 27 10 ID 26 Address: See Table 18-7 9 ID 25 8 ID 24 7 ID 23 6 ID 22 5 ID 21 4 ID 20 3 ID 19 2 ID 18 1 ID 17 0 ID 16 15 M_IDLn (n = 00 to 31) ID 15 14 ID 14 13 ID 13 12 ID 12 11 ID 11 10 ID 10 9 ID 9 8 ID 8 7 ID 7 6 ID 6 5 ID 5 4 ID 4 3 ID 3 2 ID 2 1 ID 1 0 ID 0 IDE 0 1 Specification of format setting mode Standard format mode (ID28 to ID18: 11 bits) Extended format mode (ID28 to ID0: 29 bits) User's Manual U14665EJ4V0UD 431 CHAPTER 18 FCAN CONTROLLER Table 18-7. Addresses of M_IDLn and M_IDHn (n = 00 to 31) Register Name M_IDL00 M_IDH00 M_IDL01 M_IDH01 M_IDL02 M_IDH02 M_IDL03 M_IDH03 M_IDL04 M_IDH04 M_IDL05 M_IDH05 M_IDL06 M_IDH06 M_IDL07 M_IDH07 M_IDL08 M_IDH08 M_IDL09 M_IDH09 M_IDL10 M_IDH10 M_IDL11 M_IDH11 M_IDL12 M_IDH12 M_IDL13 M_IDH13 M_IDL14 M_IDH14 M_IDL15 M_IDH15 Address (m = 3, 7, B) xxmFF810H xxmFF812H xxmFF830H xxmFF832H xxmFF850H xxmFF852H xxmFF870H xxmFF872H xxmFF890H xxmFF892H xxmFF8B0H xxmFF8B2H xxmFF8D0H xxmFF8D2H xxmFF8F0H xxmFF8F2H xxmFF910H xxmFF912H xxmFF930H xxmFF932H xxmFF950H xxmFF952H xxmFF970H xxmFF972H xxmFF990H xxmFF992H xxmFF9B0H xxmFF9B2H xxmFF9D0H xxmFF9D2H xxmFF9F0H xxmFF9F2H Register Name M_IDL16 M_IDH16 M_IDL17 M_IDH17 M_IDL18 M_IDH18 M_IDL19 M_IDH19 M_IDL20 M_IDH20 M_IDL21 M_IDH21 M_IDL22 M_IDH22 M_IDL23 M_IDH23 M_IDL24 M_IDH24 M_IDL25 M_IDH25 M_IDL26 M_IDH26 M_IDL27 M_IDH27 M_IDL28 M_IDH28 M_IDL29 M_IDH29 M_IDL30 M_IDH30 M_IDL31 M_IDH31 Address (m = 3, 7, B) xxmFFA10H xxmFFA12H xxmFFA30H xxmFFA32H xxmFFA50H xxmFFA52H xxmFFA70H xxmFFA72H xxmFFA90H xxmFFA92H xxmFFAB0H xxmFFAB2H xxmFFAD0H xxmFFAD2H xxmFFAF0H xxmFFAF2H xxmFFB10H xxmFFB12H xxmFFB30H xxmFFB32H xxmFFB50H xxmFFB52H xxmFFB70H xxmFFB72H xxmFFB90H xxmFFB92H xxmFFBB0H xxmFFBB2H xxmFFBD0H xxmFFBD2H xxmFFBF0H xxmFFBF2H 432 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.6 CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFn register is used to specify the message buffer type and mask setting (n = 00 to 31). These registers can be read/written in 8-bit units. After reset: Undefined 7 M_CONFn (n = 00 to 31) MT2 0 0 0 0 1 1 1 1 MT1 0 0 1 1 0 0 1 1 0 6 0 R/W 5 MT2 Address: See Table 18-8 4 MT1 3 MT0 2 MA2 1 MA1 0 MA0 MT0 0 1 0 1 0 1 0 1 Specification of message type and mask setting Transmit message Receive message (no mask setting) Receive message (mask 0 is set) Receive message (mask 1 is set) Receive message (mask 2 is set) Receive message (mask 3 is set) Setting prohibited Receive message (used in diagnostic processing mode) * When bits MT2 to MT0 have been set as "111", processing can be performed only when the FCAN has been set to diagnostic processing mode. In such cases, all messages received are stored regardless of the following conditions. * Storage to other message buffer * Identifier type (standard frame or extended frame) * Data frame or remote frame MA2 0 0 0 MA1 0 0 1 Other than above MA0 0 1 0 Message buffer's address specification Message buffer is not used Used as message buffer of CAN module 1 Used as message buffer of CAN module 2 Setting prohibited Note * When the MA2, MA1, and MA0 bits have been set to "000", message buffer area is used for application RAM or for event processing as a temporary buffer. * In the unused message buffers, always set the MA2, MA1, and MA0 bits to 000. Note PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y only User's Manual U14665EJ4V0UD 433 CHAPTER 18 FCAN CONTROLLER Table 18-8. Addresses of M_CONFn (n = 00 to 31) Register Name M_CONF00 M_CONF01 M_CONF02 M_CONF03 M_CONF04 M_CONF05 M_CONF06 M_CONF07 M_CONF08 M_CONF09 M_CONF10 M_CONF11 M_CONF12 M_CONF13 M_CONF14 M_CONF15 Address (m = 3, 7, B) xxmFF814H xxmFF834H xxmFF854H xxmFF874H xxmFF894H xxmFF8B4H xxmFF8D4H xxmFF8F4H xxmFF914H xxmFF934H xxmFF954H xxmFF974H xxmFF994H xxmFF9B4H xxmFF9D4H xxmFF9F4H Register Name M_CONF16 M_CONF17 M_CONF18 M_CONF19 M_CONF20 M_CONF21 M_CONF22 M_CONF23 M_CONF24 M_CONF25 M_CONF26 M_CONF27 M_CONF28 M_CONF29 M_CONF30 M_CONF31 Address (m = 3, 7, B) xxmFFA14H xxmFFA34H xxmFFA54H xxmFFA74H xxmFFA94H xxmFFAB4H xxmFFAD4H xxmFFAF4H xxmFFB14H xxmFFB34H xxmFFB54H xxmFFB74H xxmFFB94H xxmFFBB4H xxmFFBD4H xxmFFBF4H 434 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). These registers are read-only, in 8-bit units. Cautions 1. Writing directly to the M_STATn register cannot be performed. Writing must be performed using CAN status set/clear register n (SC_STATn). 2. Messages are transmitted only when the M_STATn register's TRQ and RDY bits have been set (1). After reset: Undefined 7 M_STATn (n = 00 to 31) DN 0 1 0 6 0 R 5 0 Address: See Table 18-9 4 0 3 RFU Note 1 2 DN 1 TRQ 0 RDY Note 2 Message update flag No message was received after DN bit was cleared At least one message was received after DN bit was cleared * When the DN bit has been set (1) by the transmit message buffer, it indicates that the message buffer has received a remote frame. When this message is sent, the DN bit is automatically cleared (0). * When a frame is again received in the message buffer for which the DN bit has been set (1), an overwrite condition occurs and the M_CTRLn register's MOVR bit is set (1). TRQ 0 1 Transmit request flag Message transmission prohibited Message transmission enabled * A transmit request is processed as a CAN module only when the RDY bit is set to 1. * A remote frame is transmitted to the receive message buffer in which the TRQ bit is set to 1. RDY 0 1 Message is not ready Message is ready Message ready flag * A receive operation is performed only for a message buffer in which the RDY bit is set to 1 during reception. * A transmit operation is performed only for a message buffer in which the RDY bit is set to 1 and the TRQ bit is set to 1 during transmission. Notes 1. RFU (Reserved for Future Use) indicates a reserved bit. 0 or 1 is read from this bit regardless of the message buffer setting. 2. The FCAN controller incorporated in the V850/SF1 can perform reception even if the RDY bit is not set. However, in products other than the V850/SF1, the RDY bit must be set for reception. In order to maintain software compatibility, be sure to set the RDY bit even for the FCAN controller of the V850/SF1 prior to reception. User's Manual U14665EJ4V0UD 435 CHAPTER 18 FCAN CONTROLLER Table 18-9. Addresses of M_STATn (n = 00 to 31) Register Name M_STAT00 M_STAT01 M_STAT02 M_STAT03 M_STAT04 M_STAT05 M_STAT06 M_STAT07 M_STAT08 M_STAT09 M_STAT10 M_STAT11 M_STAT12 M_STAT13 M_STAT14 M_STAT15 Address (m = 3, 7, B) xxmFF815H xxmFF835H xxmFF855H xxmFF875H xxmFF895H xxmFF8B5H xxmFF8D5H xxmFF8F5H xxmFF915H xxmFF935H xxmFF955H xxmFF975H xxmFF995H xxmFF9B5H xxmFF9D5H xxmFF9F5H Register Name M_STAT16 M_STAT17 M_STAT18 M_STAT19 M_STAT20 M_STAT21 M_STAT22 M_STAT23 M_STAT24 M_STAT25 M_STAT26 M_STAT27 M_STAT28 M_STAT29 M_STAT30 M_STAT31 Address (m = 3, 7, B) xxmFFA15H xxmFFA35H xxmFFA55H xxmFFA75H xxmFFA95H xxmFFAB5H xxmFFAD5H xxmFFAF5H xxmFFB15H xxmFFB35H xxmFFB55H xxmFFB75H xxmFFB95H xxmFFBB5H xxmFFBD5H xxmFFBF5H 436 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.8 CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31) The SC_STATn register is used to set/clear the transmit/receive status information (n = 00 to 31). These registers are write-only, in 16-bit units. After reset: 0000H 15 SC_STATn (n = 00 to 31) 7 0 6 0 0 14 0 W 13 0 Address: See Table 18-10 12 0 11 0 10 set DN 9 set TRQ 8 set RDY 5 0 4 0 3 0 2 clear DN 1 0 clear TRQ clear RDY set DN 0 1 clear DN 1 0 Clear (Clear DN bit) Set (Set DN bit) Message update flag setting Other than above No change in DN bit value set TRQ 0 1 clear TRQ 1 0 Transmit request flag setting Clear (Clear TRQ bit) Set (Set TRQ bit) No change in TRQ bit value Other than above set RDY 0 1 clear RDY 1 0 Clear (Clear RDY bit) Set (Set RDY bit) Message ready flag setting Other than above No change in RDY bit value Remark DN: Bit 2 of CAN message status register n (M_STATn) TRQ: Bit 1 of CAN message status register n (M_STATn) RDY: Bit 0 of CAN message status register n (M_STATn) User's Manual U14665EJ4V0UD 437 CHAPTER 18 FCAN CONTROLLER Table 18-10. Addresses of SC_STATn (n = 00 to 31) Register name SC_STAT00 SC_STAT01 SC_STAT02 SC_STAT03 SC_STAT04 SC_STAT05 SC_STAT06 SC_STAT07 SC_STAT08 SC_STAT09 SC_STAT10 SC_STAT11 SC_STAT12 SC_STAT13 SC_STAT14 SC_STAT15 Address (m = 3, 7, B) xxmFF816H xxmFF836H xxmFF856H xxmFF876H xxmFF896H xxmFF8B6H xxmFF8D6H xxmFF8F6H xxmFF916H xxmFF936H xxmFF956H xxmFF976H xxmFF996H xxmFF9B6H xxmFF9D6H xxmFF9F6H Register name SC_STAT16 SC_STAT17 SC_STAT18 SC_STAT19 SC_STAT20 SC_STAT21 SC_STAT22 SC_STAT23 SC_STAT24 SC_STAT25 SC_STAT26 SC_STAT27 SC_STAT28 SC_STAT29 SC_STAT30 SC_STAT31 Address (m = 3, 7, B) xxmFFA16H xxmFFA36H xxmFFA56H xxmFFA76H xxmFFA96H xxmFFAB6H xxmFFAD6H xxmFFAF6H xxmFFB16H xxmFFB36H xxmFFB56H xxmFFB76H xxmFFB96H xxmFFBB6H xxmFFBD6H xxmFFBF6H 438 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.9 CAN interrupt pending register (CCINTP) The CCINTP register is used to confirm the pending status of various interrupts. This register is read-only, in 16-bit units. After reset: 0000H 15 CCINTP 0 7 0 14 INTMAC 6 0 R 13 0 5 Address: xxmFFC00H (m = 3, 7, B) 12 0 4 11 0 3 10 0 2 9 0 1 8 0 0 CAN2ERR CAN2REC CAN2TRX CAN1ERR CAN1REC CAN1TRX INTMAC 0 1 Pending status of MAC error Not pending Pending Note 1 interrupts (GINT3 to GINT1) CAN2ERR 0 1 Note 2 Pending status of CAN2 access error interrupt (C2INT6 to C2INT2) Not pending Pending CAN2REC 0 1 Note 2 Pending status of CAN2 receive completion interrupt (C2INT1) Not pending Pending CAN2TRX 0 1 Note 2 Pending status of CAN2 transmit completion interrupt (C2INT0) Not pending Pending CAN1ERR 0 1 Pending status of CAN1 access error interrupt (C1INT6 to C1INT2) Not pending Pending CAN1REC 0 1 Pending status of CAN1 receive completion interrupt (C1INT1) Not pending Pending CAN1TRX 0 1 Pending status of CAN1 transmit completion interrupt (C1INT0) Not pending Pending Notes 1. MAC (Memory Access Control) errors are errors that are set only when an interrupt source has occurred for the CAN global interrupt pending register (CGINTP). 2. PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y only Remark GINT3 to GINT1: Bits 3 to 1 of the CAN global interrupt pending register (CGINTP) CnINT6 to CnINT0 (n = 1, 2): Bits 6 to 0 of the CANn interrupt pending register (CnINTP) User's Manual U14665EJ4V0UD 439 CHAPTER 18 FCAN CONTROLLER 18.4.10 CAN global interrupt pending register (CGINTP) The CGINTP register is used to confirm the pending status of MAC access error interrupts. This register can be read/written in 16-bit or 8-bit units. Cautions 1. When "1" is written to a bit in the CGINTP register, that bit is cleared (0). When "0" is written to it, the bit's value does not change. 2. An interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. The timing of setting the interrupt pending bit (1) is controlled by an interrupt service routine. The earlier that the interrupt service routine clears the interrupt pending bit (0), the more quickly the interrupt occurs without losing any new interrupts of the same type. The interrupt pending bit can be set (1) only when the interrupt enable bit has been set (1). However, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). Use software processing to clear the interrupt pending bit (0). Remark For details of invalid write access error interrupts and unavailable memory address access error interrupts, see 18.15.2 Interrupts that occur for global CAN interface. After reset: 0000H 15 CGINTP 0 7 0 14 0 6 0 R/W 13 0 5 0 Address: xxmFFC02H (m = 3, 7, B) 12 0 4 0 11 0 3 GINT3 10 0 2 GINT2 9 0 1 GINT1 8 0 0 0 GINT3 Pending status of wakeup interrupt (from CAN sleep mode with clock supply to FCAN stopped) 0 1 Not pending Pending GINT2 0 1 Not pending Pending Pending status of invalid write access error interrupt GINT1 0 1 Pending status of unavailable memory address access error interrupt Not pending Pending 440 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.11 CANn interrupt pending register (CnINTP) The CnINTP register is used to confirm the pending status of interrupts issued to the CAN. This register can be read/written in 16-bit or 8-bit units. The CAN2 interrupt pending register (C2INTP) is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. When "1" is written to a bit in the CnINTP register, that bit is cleared (0). When "0" is written to it, the bit's value does not change. 2. An interrupt occurs when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (1) for a new interrupt. The timing of setting the interrupt pending bit (1) is controlled by an interrupt service routine. The earlier that the interrupt service routine clears the interrupt pending bit (0), the more quickly the interrupt occurs without losing any new interrupts of the same type. The interrupt pending bit can be set (1) only when the interrupt ready bit has been set (1). However, the interrupt pending bit is not automatically cleared (0) just because the interrupt enable bit has been cleared (0). Use software processing to clear the interrupt pending bit (0). Remark n = 1, 2 User's Manual U14665EJ4V0UD 441 CHAPTER 18 FCAN CONTROLLER After reset: 0000H 15 CnINTP (n = 1, 2) 0 7 0 14 0 6 CnINT6 R/W 13 0 5 CnINT5 Addresses: C1INTP: xxmFFC04H (m = 3, 7, B) C2INTP: xxmFFC06H (m = 3, 7, B) 12 0 4 CnINT4 11 0 3 CnINT3 10 0 2 CnINT2 9 0 1 CnINT1 8 0 0 CnINT0 CnINT6 0 1 Not pending Pending Pending status of CAN error interrupt CnINT5 0 1 Not pending Pending Pending status of CAN bus error interrupt CnINT4 0 1 Pending status of wakeup interrupt (from CAN sleep mode) Not pending Pending CnINT3 0 1 Pending status of CAN receive error passive status interrupt Not pending Pending CnINT2 0 1 Pending status of CAN transmit error passive or bus off status interrupt Not pending Pending CnINT1 0 1 Not pending Pending Pending status of CAN receive completion interrupt CnINT0 0 1 Not pending Pending Pending status of CAN transmit completion interrupt 442 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.12 CAN stop register (CSTOP) The CSTOP register controls clock supply to the entire CAN system. This register can be read/written in 16-bit units. Cautions 1. Be sure to set the CSTP bit (1) if the FCAN function will not be used. 2. When the CSTP bit is set (1), access to FCAN registers other than the CSTOP register is prohibited. Access to FCAN (other than the CSTOP register) is possible only when the CSTP bit is not set (1). 3. When a change occurs on the CAN bus via a CSTP setting while the clock supply to the CPU or peripheral functions is stopped, the CPU can be woken up. 4. If the CAN main clock (fMEM1) is stopped in other than CAN sleep mode, first set the CAN module to initial mode (INIT bit of CnCTRL register = 1), clear (0) the GOM bit of the CGST register, and then set (1) the CSTP bit. After reset: 0000H 15 CSTOP CSTP 14 0 13 0 12 0 R/W 11 0 10 0 Address: xxmFFC0CH (m = 3, 7, B) 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 CSTP 0 1 Controls clock supply to FCAN FCAN in operation (clock supplied to FCAN blocks) FCAN is stopped (access to FCAN blocks is not possible) User's Manual U14665EJ4V0UD 443 CHAPTER 18 FCAN CONTROLLER 18.4.13 CAN global status register (CGST) The CGST register indicates global status information. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 Cautions Regarding Bit Set/Clear Function. 2. When writing to the CGST register, set or clear bits according to the register configuration shown in part (b) Write of the following figure. (1/3) After reset: 0100H (a) Read CGST 15 0 7 MERR 14 0 6 0 R/W 13 0 5 0 Address: xxmFFC10H (m = 3, 7, B) 12 0 4 0 11 0 3 EFSD 10 0 2 TSM 9 0 1 0 8 1 0 GOM (b) Write CGST 15 0 7 clear MERR 14 0 6 0 13 0 5 0 12 0 4 0 11 set EFSD 3 10 set TSM 2 9 0 1 0 8 set GOM 0 clear GOM clear EFSD clear TSM (a) Read MERR 0 1 MAC error status flag Error does not occur after the MERR bit has been cleared Error occurs at least once after MERR bit has been cleared * MAC errors occur under the following conditions. * When invalid address is accessed * When access prohibited by MAC is performed * When the GOM bit is cleared (0) before the INIT bit of the CnCTRL register is set (1) EFSD 0 1 Shutdown prohibited Shutdown enabled Shutdown request * Be sure to set the EFSD bit (1) before clearing the GOM bit (0) (must be accessed twice). The EFSD bit will be cleared (0) automatically when the CGST register is accessed again. TSM 0 1 Operation status of time stamp counter Time stamp counter is stopped Time stamp counter is operating Note Note See 18.4.16 CAN time stamp count register (CGTSC). 444 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (2/3) (a) Read GOM 0 1 Status of global operation mode Access to CAN module register Access to CAN module register Note 1 is prohibited is enabled Note 1 * The GOM bit controls the method the memory is accessed by the MAC and CAN module operation state. * When GOM bit = 0 * All the CAN modules are reset. * Access to CAN module register disabled (if accessed, MAC error interrupt occurs) * Read/write access to temporary buffer enabled * Access to message buffer area enabled * When GOM bit = 1 * Access to CAN module register enabled occurs) * Access to message buffer area enabled * The GOM bit is cleared (0) only when all the CAN modules are in the initial status (the ISTAT bit of the CnCTR register is 1). Even if the GOM bit is cleared when there is a CAN module not in the initial status, the GOM bit remains set (1). * To clear (0) the GOM bit, first set (1) the INIT bit of the CnCTRL register, and then set (1) the EFSD bit. Do not manipulate the GOM bit and EFSD bit simultaneously. Note 3 Note 2 * Access to temporary buffer prohibited (if access is attempted, MAC error interrupt Notes 1. Register with a name starting with "Cn" (n = 1, 2) 2. The CGCS register can be accessed. Write accessing the CGMSS register is prohibited. If the CGMSS register is writeaccessed, the wrong search result is reflected in the CGMSR register. 3. Write-accessing the CGCS register is prohibited. Write-accessing the CGMSS register is possible. User's Manual U14665EJ4V0UD 445 CHAPTER 18 FCAN CONTROLLER (3/3) (b) Write set EFSD clear EFSD 0 1 1 0 EFSD bit cleared EFSD bit set No change in value of EFSD bit EFSD bit enable Other than above set TSM 0 1 clear TSM 1 0 TSM bit cleared TSM bit set TSM bit enable Other than above No change in value of TSM bit set GOM clear GOM 0 1 1 0 GOM bit cleared GOM bit set GOM bit enable Other than above No change in value of GOM bit clear MERR 0 1 MERR bit enable No change in value of MERR bit MERR bit cleared 446 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.14 CAN global interrupt enable register (CGIE) The CGIE register is used to issue interrupt requests for global interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 Cautions Regarding Bit Set/Clear Function. 2. When writing to the CGIE register, set or clear bits according to the register configuration shown in part (b) Write of the following figure. After reset: 0A00H (a) Read CGIE 15 0 7 0 14 0 6 0 R/W 13 0 5 0 Address: xxmFFC12H (m = 3, 7, B) 12 0 4 0 11 1 3 0 10 0 2 G_IE2 9 1 1 G_IE1 8 0 0 0 (b) Write CGIE 15 0 7 0 14 0 6 0 13 0 5 0 12 0 4 0 11 0 3 0 10 9 8 0 0 0 set G_IE2 set G_IE1 2 clear G_IE2 1 clear G_IE1 (a) Read G_IE2 0 1 Interrupt enable status for invalid write access (to temporary buffer, etc.) Interrupt disabled Interrupt enabled G_IE1 0 1 Interrupt enable status for memory access to reserved address Interrupt disabled Interrupt enabled (b) Write set G_IEn clear G_IEn 0 1 1 0 Clear G_IEn bit Set G_IEn bit No change Setting of G_IEn bit Other than above Remark n = 1, 2 User's Manual U14665EJ4V0UD 447 CHAPTER 18 FCAN CONTROLLER 18.4.15 CAN main clock selection register (CGCS) The CGCS register is used to select the main clock. This register can be read/written in 16-bit units. Caution When the GOM bit of the CGST register is 1, write accessing the CGCS register is prohibited. After reset: 7F05H 15 CGCS CGTS7 7 GTCS1 14 CGTS6 6 GTCS0 R/W 13 CGTS5 5 0 Address: xxmFFC14H (m = 3, 7, B) 12 CGTS4 4 0 Note 1 11 CGTS3 3 MCP3 10 CGTS2 2 MCP2 9 CGTS1 1 MCP1 8 CGTS0 0 MCP0 n CGTS CGTS CGTS CGTS CGTS CGTS CGTS CGTS 7 6 5 4 3 2 1 0 System timer prescaler selection fGTS = fGTS1 / (n + 1) 0 1 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 1 fGTS = fGTS1/1 fGTS = fGTS1/2 fGTS = fGTS1/(n + 1) 127 0 1 1 1 : 1 1 1 1 fGTS = fGTS1/128 (after reset) fGTS = fGTS1/(n + 1) 254 255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 fGTS = fGTS1/255 fGTS = fGTS1/256 Note 2 The global time system clock (fGTS) is the source clock for the time stamp counter used for the time stamp function. that is GTCS1 0 0 1 1 GTCS0 0 1 0 1 fMEM/2 fMEM/4 fMEM/8 fMEM/16 Global timer clock selection (fGTS1) n 0 1 2 MCP3 MCP2 MCP1 MCP0 0 0 0 0 0 0 : 0 0 1 0 1 0 Selection of clock to memory access controller (fMEM) fMEM1 fMEM1/2 fMEM1/3 14 15 1 1 1 1 1 1 0 1 fMEM1/15 fMEM1/16 Once the values of the MCP3 to MCP0 bits are set after reset is released, do not change these values. Notes 1. When writing to this bit, always set it to 0. 2. See 18.4.16 CAN time stamp count register (CGTSC). 448 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-2. FCAN Clocks FCAN main clock select register (CGCS) CGTS7 CGTS6 CGTS5 CGTS4 CGTS3 CGTS2 CGTS1 CGTS0 GTCS1 GTCS0 MCP3 MCP2 MCP1 MCP0 fMEM1 Prescaler fMEM Global timer clock prescaler fGTS1 Global timer system clock fGTS Time stamp counter fBTL Baud rate generator CANn synchronization control register (CnSYNC) Data bit time BTYPE BRP7Note BRP6Note BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CANn bit rate prescaler register (CnBRP) Note When the TLM bit of the CANn bit rate prescaler register (CnBRP) is 1. Caution When using a 1 Mbps transfer rate for the CPU, input fMEM1 as a 16 MHz clock signal. If input at another frequency, subsequent operation is not guaranteed. Remark fMEM1 = fXX = Clock supplied to CAN User's Manual U14665EJ4V0UD 449 CHAPTER 18 FCAN CONTROLLER 18.4.16 CAN time stamp count register (CGTSC) The CGTSC register indicates the contents of the time stamp counter. This register can be read at any time. This register can be written to only when clearing bits. The clear function writes 0 to all bits in the CGTSC register. This register is read-only, in 16-bit units. After reset: 0000H 15 CGTSC TSC15 7 TSC7 14 TSC14 6 TSC6 R 13 TSC13 5 TSC5 Address: xxmFFC18H (m = 3, 7, B) 12 TSC12 4 TSC4 11 TSC11 3 TSC3 10 TSC10 2 TSC2 9 TSC9 1 TSC1 8 TSC8 0 TSC0 450 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.17 CAN message search start/result register (CGMSS/CGMSR) The CGMSS/CGMSR register indicates the message search start/result status. Messages in the message buffer that match the specified search criteria can be searched quickly. These registers can be read/written in 16-bit units. Cautions 1. Execute a search by writing the CGMSS register only once. 2. Be sure to set the SMNO2 bit of the CGMSS register to 0. guaranteed. (1/2) After reset: 0000H (a) Read CGMSR 15 0 7 0 14 0 6 0 R/W 13 0 5 0 Address: xxmFFC1AH (m = 3, 7, B) 12 0 4 MFND4 11 0 3 MFND3 10 0 2 MFND2 9 MM 1 MFND1 8 AM 0 MFND0 If 1 is set, operation is not (b) Write CGMSS 15 CIDE 7 0 14 0 6 0 13 CTRQ 5 0 12 CMSK 4 STRT4 11 CDN 3 STRT3 10 SMNO2 2 STRT2 9 SMNO1 1 STRT1 8 SMNO0 0 STRT0 (a) Read MM 0 1 Confirmation of multiple hits from message search No messages or only one message meets the search criteria Several messages meet the search criteria If several message buffers that meet the search criteria are detected, the MM bit is set. AM 0 1 Confirmation of hits from message search No messages meet the search criteria At least one message meets the search criteria MFND4 to MFND0 Searched message number This indicates the number (0 to 31) of the searched message. * When multiple message buffer numbers match as a result of a search (MM = 1), the return value of bits MFND4 to MFND0 is the lowest message buffer number. When no message buffer numbers match (AM = 0), the return value of bits MFND4 to MFND0 is "message buffer number -1". User's Manual U14665EJ4V0UD 451 CHAPTER 18 FCAN CONTROLLER (2/2) (b) Write CIDE 0 1 Message identifier (ID) format flag check Message identifier format flag not checked Message with standard format identifier checked CTRQ 0 1 Transmit request and message ready flag check Transmit request and message ready flags not checked Transmit request and message ready flags checked CMSK 0 1 Masked message check Masked messages not checked Only masked messages checked CDN 0 1 Status check of M_STATn register's DN flag (n = 00 to 31) Status of M_STATn register's DN flag not checked Status of M_STATn register's DN flag checked SMNO2 0 0 0 SMNO1 0 0 1 Other SMNO0 0 1 0 Search module setting No search module setting CAN module 1 is set as the searched target CAN module 2 is set as the searched target Setting prohibited STRTn 0 to 31 Message search start position (n = 0 to 4) Message search start position (message number) * Search starts from the message number defined by the STRT4 to STRT0 bits. Search continues until it reaches the message buffer having the highest number among the usable message buffers. If the search results include several message buffer numbers among the matching messages, the message buffer with the lowest message buffer number is selected. To fetch the next message buffer number without changing the search criteria, "(MFND4 to MFND0) + 1" must be set as the values of bits STRT4 to STRT0. 452 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) The CnMASKLa and CnMASKHa registers are used to extend the number of receivable messages by masking part of the message's identifier (ID) and then ignoring the masked parts. These registers can be read/written in 16-bit units. The C2MASKLa and C2MASKHa registers are valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y (a = 0 to 3). Cautions 1. When the receive message buffer is linked to the CnMASKLa and CnMASKHa registers, regardless of whether the ID in the receive message buffer is a standard ID (11 bits) or an extended ID (29 bits), set all the 32-bit values of the CnMASKLa and CnMASKHa registers (a = 0 to 3, n = 1, 2). 2. When the CnMASKLa and CnMASKHa registers are linked to the message buffer for standard IDs, the lower 18 bits of the data field in the data frame are also automatically compared. Therefore, if it is not necessary to compare the lower 18 bits (masking), set (1) the CMID17 to CMID0 bits (a = 0 to 3, n = 1, 2). The standard ID and extended ID can use the same mask. After reset: Undefined 15 CnMASKHa (a = 0 to 3, n = 1, 2) CMIDE 7 CMID23 15 CnMASKLa (a = 0 to 3, n = 1, 2) CMID15 7 CMID7 14 0 6 CMID22 14 CMID14 6 CMID6 R/W 13 0 5 CMID21 13 CMID13 5 CMID5 Address: See Table 18-11 12 CMID28 4 CMID20 12 CMID12 4 CMID4 11 CMID27 3 CMID19 11 CMID11 3 CMID3 10 CMID26 2 CMID18 10 CMID10 2 CMID2 9 CMID25 1 CMID17 9 CMID9 1 CMID1 8 CMID24 0 CMID16 8 CMID8 0 CMID0 CMIDE 0 1 Mask setting for identifier (ID) format ID format (standard or extended) checked ID format (standard or extended) not checked When the CMIDE bit is set (1), the higher 11 bits of the ID are compared. The receive message and the ID format stored in a message buffer are not compared. CMID0 to CMID28 0 Mask setting for identifier (ID) bits ID bit in message buffer linked to bits CMID28 to CMID0 compared with received ID bit. 1 ID bit in message buffer linked to bits CMID28 to CMID0 not compared with received ID bit (i.e., masked). User's Manual U14665EJ4V0UD 453 CHAPTER 18 FCAN CONTROLLER Table 18-11. Addresses of CnMASKLa and CnMASKHa (a = 0 to 3, n = 1, 2) Register Name C1MASKL0 C1MASKH0 C1MASKL1 C1MASKH1 C1MASKL2 C1MASKH2 C1MASKL3 C1MASKH3 Address (m = 3, 7, B) xxmFFC40H xxmFFC42H xxmFFC44H xxmFFC46H xxmFFC48H xxmFFC4AH xxmFFC4CH xxmFFC4EH Register Name C2MASKL0 C2MASKH0 C2MASKL1 C2MASKH1 C2MASKL2 C2MASKH2 C2MASKL3 C2MASKH3 Address (m = 3, 7, B) xxmFFC80H xxmFFC82H xxmFFC84H xxmFFC86H xxmFFC88H xxmFFC8AH xxmFFC8CH xxmFFC8EH 454 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.19 CANn control register (CnCTRL) The CnCTRL register is used to control the operation of the CAN module. This register can be read/written in 16-bit units. The C2CTRL register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. Both bitwise writing and direct writing to the CnCTRL register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 Cautions Regarding Bit Set/Clear Function. 2. When writing to the CnCTRL register, set or clear bits according to the register configuration shown in part (b) Write of the following figure. 3. When releasing CAN stop mode, CAN sleep mode must be released at the same time. (1/4) After reset: 0101H (a) Read CnCTRL (n = 1, 2) 15 TECS1 7 0 14 TECS0 6 DLEVR R/W 13 RECS1 5 DLEVT Addresses: C1CTRL: xxmFFC50H (m = 3, 7, B) C2CTRL: xxmFFC90H (m = 3, 7, B) 12 RECS0 4 OVM 11 BOFF 3 TMR 10 TSTAT 2 STOP 9 RSTAT 1 SLEEP 8 ISTAT 0 INIT (b) Write CnCTRL (n = 1, 2) 15 0 7 0 14 13 12 11 set TMR 3 10 9 8 set INIT 0 set DLEVR set DLEVT set OVM 6 5 4 set STOP set SLEEP 2 1 clear DLEVR clear DLEVT clear OVM clear TMR clear STOP clear SLEEP clear INIT (a) Read TECS1 0 0 1 1 TECS0 0 1 0 1 Status of transmit error counter Transmit error counter value < 96 Transmit error counter value = 96 to 127 (warning level) Not used Transmit error counter value 128 (error passive) RECS1 0 0 1 1 RECS0 0 1 0 1 Status of receive error counter Receive error counter value < 96 Receive error counter value = 96 to 127 (warning level) Not used Receive error counter value 128 (error passive) BOFF 0 1 Bus off flag Transmit error counter value < 256 (not bus off status) Transmit error counter value 256 (bus off status) User's Manual U14665EJ4V0UD 455 CHAPTER 18 FCAN CONTROLLER (2/4) (a) Read TSTAT 0 1 Transmit stop status Transmit operating status Transmit status flag RSTAT 0 1 Receive stop status Receive operating status Receive status flag ISTAT 0 1 Normal operating status Initialization status flag FCAN is stopped and initialized * The ISTAT bit is set (1) when the CAN protocol layer acknowledges the setting of the INIT bit and STOP bit. The ISTAT bit is automatically cleared (0) after the INIT bit and STOP bit are cleared (0). * When the ISTAT bit has been set (1): "receive" is output via the CANTXn pin during initialization mode. * The CnSYNC and CnBRP registers can be written only during initialization mode. * In the initialization status, the error counter (see 18.4.22 CANn error count register (CnERC)) is cleared (0) and the error status (bit TECS1, TECS0, RECS1, and RECS0) is reset. DLEVR 0 1 Dominant level control bit for receive pin A low level to a receive pin is acknowledged as dominant A high level to a receive pin is acknowledged as dominant DLEVT 0 1 Dominant level control bit for transmit pin A low level is transmitted from transmit pin as dominant A high level is transmitted from transmit pin as dominant OVM 0 1 Overwrite mode control bit New messages stored in message buffer in which DN bit of M_STATa register is set (a = 00 to 31) New messages in message buffer in which DN bit is set (a = 00 to 31) discarded TMR Time stamp control bit for reception The specification for the TMR bit differs depending on the product. See 18.4.19 (1) TMR bit setting. 456 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (3/4) (a) Read STOP 0 1 No CAN stop mode setting CAN stop mode CAN stop mode control bit * CAN stop mode can be selected only when the CAN module has been set to CAN sleep mode, i.e., when the SLEEP bit has been set (1). CAN stop mode can be released only by the CPU by clearing the STOP bit (0). SLEEP 0 1 Normal operating mode CAN sleep mode control bit Switch to CAN sleep mode (change in CAN bus performs wakeup) * CAN sleep mode can be set only when the CAN bus is in the idle state. * CAN sleep mode is released under the following conditions. * When the CPU has cleared the SLEEP bit (0) * When the CAN bus changes (this occurs only when CAN stop mode has not been set) Note * The WAKE bit is set (1) only when CAN sleep mode is released by the change of the CAN bus, and an error interrupt occurs. INIT 0 1 Normal operating mode Initialization mode Initialization request bit * Be sure to confirm that the CAN module has entered the initialization mode using the ISTAT bit (ISTAT bit = 1) after setting the INIT bit (1). When the ISTAT bit = 0, set the INIT bit again. * If the INIT bit is set (1) when the CAN module is in the bus off status (BOFF bit = 1), the CAN module enters initialization mode (ISTAT bit = 1) after returning from the bus off status (BOFF bit = 0). Note See 18.4.20 CANn definition register (CnDEF). User's Manual U14665EJ4V0UD 457 CHAPTER 18 FCAN CONTROLLER (4/4) (b) Write set DLEVR 0 1 clear DLEVR 1 0 DLEVR bit cleared DLEVR bit set DLEVR bit not changed DLEVR bit setting Other than above set DLEVT 0 1 clear DLEVT 1 0 DLEVT bit cleared DLEVT bit set DLEVT bit not changed DLEVT bit setting Other than above set OVM 0 1 clear OVM 1 0 OVM bit cleared OVM bit set OVM bit not changed OVM bit setting Other than above set TMR 0 1 clear TMR 1 0 TMR bit cleared TMR bit set TMR bit not changed TMR bit setting Other than above set STOP 0 1 clear STOP 1 0 STOP bit cleared STOP bit set STOP bit not changed STOP bit setting Other than above set SLEEP 0 1 clear SLEEP 1 0 SLEEP bit cleared SLEEP bit set SLEEP bit not changed SLEEP bit setting Other than above set INIT 0 1 clear INIT 1 0 INIT bit cleared INIT bit set INIT bit not changed INIT bit setting Other than above 458 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (1) TMR bit setting (a) PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY TMR 0 1 Time stamp control bit for reception Time stamp counter value not captured. Time stamp counter value captured when the EOF is detected on the CAN bus (a valid message is confirmed). (b) PD703078Y, 703079Y, 70F3079Y TMR 0 Time stamp control bit for reception Time stamp counter value captured when the SOF is detected on the CAN bus 1 Note Time stamp counter value captured when the EOF is detected on the CAN bus (a valid message is confirmed). Note When two FCAN channels are simultaneously used and the time stamp function using SOF detection at message reception is used in the PD703079Y and 70F3079Y, the following software countermeasures should be taken. * Do not set mask 2 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 100) or mask 3 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 101) as the receive buffer in the receive buffer mask setting. * Prohibit the use of the last message buffer (32th) on software. * Disable the interrupt of the last message buffer (32th). * Do not set three or more transmit request flags (set TRQ bit = 1 and clear TRQ bit = 0 in the SC_STAT00 to SC_STAT31 registers) of FCAN1 or FCAN2 at the same time. User's Manual U14665EJ4V0UD 459 CHAPTER 18 FCAN CONTROLLER 18.4.20 CANn definition register (CnDEF) The CnDEF register is used to define the operation of the CAN module. This register can be read/written in 16-bit units. The C2DEF register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. Both bitwise writing and direct writing to the CnDEF register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 Cautions Regarding Bit Set/Clear Function. 2. When writing to the CnDEF register, set or clear bits according to the register configuration shown in part (b) Write of the following figure. (1/3) After reset: 0000H (a) Read CnDEF (n = 1, 2) 15 0 7 DGM 14 0 6 MOM R/W 13 0 5 SSHT Addresses: C1DEF: xxmFFC52H (m = 3, 7, B) C2DEF: xxmFFC92H (m = 3, 7, B) 12 0 4 PBB 11 0 3 BERR 10 0 2 VALID 9 0 1 WAKE 8 0 0 OVR (b) Write CnDEF (n = 1, 2) 15 set DGM 7 14 set MOM 6 13 set SSHT 5 12 set PBB 4 11 0 3 10 0 2 9 0 1 8 0 0 clear DGM clear MOM clear SSHT clear PBB clear BERR clear VALID clear WAKE clear OVR (a) Read DGM 0 1 Specification of diagnostic processing mode Valid messages received using message buffer used for diagnostic processing Note mode (only when receiving) Valid messages received using normal operating mode (only when receiving) * The diagnostic processing mode (MOM bit = 1) is used for CAN baud rate detection and for diagnostic purposes. When this mode has been set, the following operations are performed. * When the VALID bit = 1, it indicates that the current receive operation is valid. * Setting the DGM bit confirms whether or not valid data has been stored in the message buffer used for diagnostic processing mode, the same as for normal operating mode. Note Bits 5 to 3 (MT2 to MT0) of CAN message configuration register a (M_CONFa) are set as "111" (a = 00 to 31). 460 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (2/3) (a) Read MOM 0 1 Specification of CAN module's operating mode Normal operating mode Diagnostic processing mode * When in diagnostic processing mode (MOM bit = 1), the CnBRP register can be accessed only when the CAN module has been set to initialization mode (i.e., when the CnCTRL register's ISTAT bit = INIT bit = 1). When the CAN module is operating (i.e., when the CnCTRL register's ISTAT bit = 0) the CnBRP register cannot be used, and the CANn bus diagnostic information register (CnDINF) register can be used instead. * The CAN protocol layer does not send ACK, error frame, or transmit messages, nor does it operate an error counter. The internal transmit output is fed back to the internal input due to auto baud rate detection. SSHT 0 1 Normal operating mode Single shot mode Specification of single shot mode * During single shot mode, the CAN module can transmit a message only one time. The M_STATa (a = 00 to 31) register's TRQ bit is then cleared (0) regardless of whether or not there are any pending normal transmit operations. Also, if a bus error has occurred due to a transmission, it is handled as an incomplete transmission. * During single shot mode, even if the CAN lost in arbitration, it is handled as a completed message transmission. When in this mode, the BERR bit is set (1) but the error counter value does not change since there are no CAN bus errors. * In single shot mode, even when transmission is stopped due to error detection or a loss in the arbitration phase, the transmission completion interrupt occurs. * During the time when the CAN module is active, the CPU switches between normal operating mode and single shot mode without causing any errors to occur on the CAN bus. PBB 0 1 Specification of priority control for transmission Identifier (ID) based priority control Message number based priority control * Ordinarily, priority for transmission is defined based on message IDs, but when the PBB bit has been set (1) priority becomes based instead on the position of messages, so that messages with lower message numbers have higher priority. BERR 0 1 VALID 0 1 WAKE 0 1 Normal operation Release CAN sleep mode CAN bus error status CAN bus error was not detected CAN bus error was detected at least once after bit was cleared Valid message detection status Valid message was not detected Valid message was detected at least once after bit was cleared CAN sleep mode release status * The WAKE bit is set (1) only when the CAN sleep mode is released due to a change in the CAN bus and an error interrupt occurs. * While the WAKE bit is set (1), the error interrupt signal holds the active status. Therefore, always clear (0) the WAKE bit after recognition. User's Manual U14665EJ4V0UD 461 CHAPTER 18 FCAN CONTROLLER (3/3) (a) Read OVR 0 1 Normal operation Overwrite occurred during RAM access Overrun error status * When an overrun error has occurred, the OVR bit is set (1) and an error interrupt occurs at the same time. The source of the overrun error may be that the RAM access clock is slower than the selected CAN baud rate. (b) Write set DGM clear DGM 0 1 1 0 DGM bit cleared DGM bit set DGM bit not changed DGM bit setting Other than above set MOM clear MOM 0 1 1 0 MOM bit cleared MOM bit set MOM bit not changed MOM bit setting Other than above set SSHT clear SSHT 0 1 1 0 SSHT bit cleared SSHT bit set SSHT bit not changed SSHT bit setting Other than above set PBB 0 1 clear PBB 1 0 PBB bit cleared PBB bit set PBB bit not changed PBB bit setting Other than above clear BERR 1 0 BERR bit cleared BERR bit not changed BERR bit setting clear VALID 1 0 VALID bit cleared VALID bit not changed VALID bit setting clear WAKE 1 0 WAKE bit cleared WAKE bit not changed WAKE bit setting clear OVR 1 0 OVR bit cleared OVR bit not changed OVR bit setting 462 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.21 CANn information register (CnLAST) The CnLAST register indicates the CANn module's error information and the number of the message buffer received last. This register is read-only, in 16-bit units. The C2LAST register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. After reset: 00FFH R Addresses: C1LAST: xxmFFC54H (m = 3, 7, B) C2LAST: xxmFFC94H (m = 3, 7, B) 15 CnLAST (n = 1, 2) 0 7 LREC7 14 0 6 LREC6 13 0 5 LREC5 12 0 4 LREC4 11 LERR3 3 LREC3 10 LERR2 2 LREC2 9 LERR1 1 LREC1 8 LERR0 0 LREC0 LERR3 0 0 0 0 0 0 0 LERR2 0 0 0 0 1 1 1 LERR1 0 0 1 1 0 0 1 LERR0 0 1 0 1 0 1 0 Last error information Error not detected Bit error Stuff error CRC error Form error ACK error Arbitration lost (only during single shot mode) (CnDEF: SSHT = 1) 0 1 1 0 1 0 1 0 CAN overrun error Wakeup from CAN bus Setting prohibited Other than above * Since bits LERR3 to LERR0 cannot be cleared, the current status is retained until the next error occurs. LREC7 to LREC0 0 to 31 32 to 255 Number of last receive message Message number of message last received Not used User's Manual U14665EJ4V0UD 463 CHAPTER 18 FCAN CONTROLLER 18.4.22 CANn error count register (CnERC) The CnERC register indicates the count values of the transmission/reception error counters. This register is read-only in 16-bit units. The C2ERC register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. After reset: 0000H R Addresses: C1ERC: xxmFFC56H (m = 3, 7, B) C2ERC: xxmFFC96H (m = 3, 7, B) 15 CnERC (n = 1, 2) REC7 7 TEC7 14 REC6 6 TEC6 13 REC5 5 TEC5 12 REC4 4 TEC4 11 REC3 3 TEC3 10 REC2 2 TEC2 9 REC1 1 TEC1 8 REC0 0 TEC0 REC7 to REC0 0 to 255 Reception error counter Number of reception error counts * This reflects the current status of the reception error counter. * The count value is defined by the CAN protocol. TEC7 to TEC0 0 to 255 Transmission error counter Number of transmission error counts * This reflects the current status of the transmission error counter. * The number of counts is defined by the CAN protocol. 464 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.23 CANn interrupt enable register (CnIE) The CnIE register is used to enable/disable the CAN module's interrupts. This register can be read/written in 16-bit units. The C2IE register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. Both bitwise writing and direct writing to the CnIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 18.5 Cautions Regarding Bit Set/Clear Function. 2. When writing to the CnIE register, set or clear bits according to the register configuration shown in part (b) Write of the following figure. (1/2) After reset: 0900H R/W Addresses: C1IE: xxmFFC58H (m = 3, 7, B) C2IE: xxmFFC98H (m = 3, 7, B) (a) Read CnIE (n = 1, 2) 15 0 7 0 14 0 6 E_INT6 13 0 5 E_INT5 12 0 4 E_INT4 11 1 3 E_INT3 10 0 2 E_INT2 9 0 1 E_INT1 8 1 0 E_INT0 (b) Write CnIE (n = 1, 2) 15 0 7 0 14 set E_INT6 13 set E_INT5 12 set E_INT4 11 set E_INT3 10 set E_INT2 9 set E_INT1 8 set E_INT0 6 5 4 3 2 1 0 clear E_INT6 clear E_INT5 clear E_INT4 clear E_INT3 clear E_INT2 clear E_INT1 clear E_INT0 (a) Read E_INT6 0 1 Interrupt disabled Interrupt enabled CAN module error interrupt enable flag E_INT5 0 1 Interrupt disabled Interrupt enabled CAN bus error interrupt enable flag E_INT4 0 1 Wakeup from CAN sleep mode interrupt enable flag Interrupt disabled Interrupt enabled E_INT3 0 1 Interrupt disabled Interrupt enabled Receive error passive interrupt enable flag E_INT2 0 1 Transmit error passive or bus off interrupt enable flag Interrupt disabled Interrupt enabled User's Manual U14665EJ4V0UD 465 CHAPTER 18 FCAN CONTROLLER (2/2) (a) Read E_INT1 0 1 Interrupt disabled Interrupt enabled Receive completion interrupt enable flag When IE bit of the M_CTRLn register is 1, a reception completion interrupt occurs regardless of the setting of the E_INT1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (RMDE0 bit of the M_CTRLn register = 0). E_INT0 0 1 (b) Write set E_INT6 0 1 clear E_INT6 1 0 E_INT6 interrupt cleared E_INT6 interrupt set E_INT6 interrupt not changed E_INT5 bit setting E_INT5 interrupt cleared E_INT5 interrupt set E_INT5 interrupt not changed E_INT4 bit setting E_INT4 interrupt cleared E_INT4 interrupt set E_INT4 interrupt not changed E_INT3 bit setting E_INT3 interrupt cleared E_INT3 interrupt set E_INT3 interrupt not changed E_INT2 bit setting E_INT2 interrupt cleared E_INT2 interrupt set E_INT2 interrupt not changed E_INT1 bit setting E_INT1 interrupt cleared E_INT1 interrupt set E_INT1 interrupt not changed E_INT0 bit setting E_INT0 interrupt cleared E_INT0 interrupt set E_INT0 interrupt not changed E_INT6 bit setting Interrupt disabled Interrupt enabled Transmit completion interrupt enable flag Other than above set E_INT5 0 1 clear E_INT5 1 0 Other than above set E_INT4 0 1 clear E_INT4 1 0 Other than above set E_INT3 0 1 clear E_INT3 1 0 Other than above set E_INT2 0 1 clear E_INT2 1 0 Other than above set E_INT1 0 1 clear E_INT1 1 0 Other than above set E_INT0 0 1 clear E_INT0 1 0 Other than above 466 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.24 CANn bus active register (CnBA) The CnBA register indicates frame information output via the CAN bus. This register is read-only, in 16-bit units. The C2BA register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. After reset: 00FFH R Addresses: C1BA: xxmFFC5AH (m = 3, 7, B) C2BA: xxmFFC9AH (m = 3, 7, B) 15 CnBA (n = 1, 2) 0 7 TMNO7 14 0 6 TMNO6 13 0 5 TMNO5 12 CACT4 4 TMNO4 11 CACT3 3 TMNO3 10 CACT2 2 TMNO2 9 CACT1 1 TMNO1 8 CACT0 0 TMNO0 CACT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 CACT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 CACT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 CACT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 CACT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CAN module status Reset state Bus idle wait Bus idle state Start of frame Standard identifier area Data length code area Data field area CRC field area CRC delimiter ACK slot ACK delimiter End of frame area Intermission state Suspend transmission Error frame Error delimiter wait Error delimiter Bus off error Extended identifier area Setting prohibited Other than above TMNO7 to TMNO0 0 to 31 Transmission message counter Message number of message awaiting transmission or being transmitted 32 to 254 255 Not used No messages awaiting transmission or being transmitted User's Manual U14665EJ4V0UD 467 CHAPTER 18 FCAN CONTROLLER 18.4.25 CANn bit rate prescaler register (CnBRP) The CnBRP register is used to set the transmission baud rate for the CAN module. Use the CnBRP register to select the CAN protocol layer main clock (fBTL). The baud rate is determined by the value set to the CnSYNC register. While in normal operating mode (CnDEF register's MOM bit = 0), writing to the CnBRP register is enabled only when the initialization mode has been set (CnCTRL register's INIT bit = 1). This register can be read/written in 16-bit units. The C2BRP register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Caution While in diagnostic processing mode (CnDEF register's MOM bit = 1), the CnBRP register can be accessed only when the initialization mode has been set. 468 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (1/2) After reset: 0000H R/W Addresses: C1BRP: xxmFFC5CH (m = 3, 7, B) C2BRP: xxmFFC9CH (m = 3, 7, B) (a) When TLM = 0 CnBRP (n = 1, 2) 15 TLM 7 0 14 0 6 BTYPE 13 0 5 BRP5 12 0 4 BRP4 11 0 3 BRP3 10 0 2 BRP2 9 0 1 BRP1 8 0 0 BRP0 (b) When TLM = 1 CnBRP (n = 1, 2) 15 TLM 7 BRP7 14 0 6 BRP6 13 0 5 BRP5 12 0 4 BRP4 11 0 3 BRP3 10 0 2 BRP2 9 0 1 BRP1 8 BTYPE 0 BRP0 (a) When TLM = 0 TLM 0 6-bit prescaler mode Transfer layer mode specification BTYPE 0 1 Low speed ( 125 Kbps) High speed (> 125 Kbps) CAN bus type specification a BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer base system clock (fBTL) 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 1 1 0 1 0 1 fMEM/2 fMEM/4 fMEM/6 fMEM/8 fMEM/{(a + 1) x 2} 60 61 62 63 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 fMEM/122 fMEM/124 fMEM/126 fMEM/128 Remark fBTL = fMEM/{(a + 1) x 2}: CAN protocol layer base system clock a = 0 to 63 (set by bits BRP5 to BRP0) fMEM = CAN base clock User's Manual U14665EJ4V0UD 469 CHAPTER 18 FCAN CONTROLLER (2/2) (b) When TLM = 1 TLM 1 8-bit prescaler mode Transfer layer mode specification BTYPE 0 1 Low speed ( 125 Kbps) High speed (> 125 Kbps) CAN bus type specification a BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer base system clock (fBTL) 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Setting prohibited fMEM/2 fMEM/3 fMEM/4 fMEM/(a + 1) 252 253 254 255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 fMEM/253 fMEM/254 fMEM/255 fMEM/256 Remark fBTL = fMEM/(a + 1): CAN protocol layer base system clock a = 0 to 255 (set by bits BRP7 to BRP0) fMEM = CAN base clock 470 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.4.26 CANn bus diagnostic information register (CnDINF) The CnDINF register indicates all the CAN bus bits, including the stuff bits and delimiters. This information is used only for diagnostic purposes. Because the number of bits starting from SOF is added at each frame, the actual number of bits is the value obtained by subtracting the previous data. This register is read-only in 16-bit units. The C2DINF register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. The CnDINF register can be accessed only while in diagnostic processing mode (CnDEF register's MOM bit = 1) and in the normal operating mode of the CANn control register (CnCTRL register's INIT bit = 0). In normal operating mode of the CANn definition register (CnDEF register's MOM bit = 0), this register cannot be accessed. 2. Storage of the last 8 bits is automatically stopped if an error or a valid message (ACK delimiter) is detected on the CAN bus. Storage is automatically reset each time when SOF is detected on the CAN bus. After reset: 0000H R Addresses: C1DINF: xxmFFC5CH (m = 3, 7, B) C2DINF: xxmFFC9CH (m = 3, 7, B) 15 CnDINF (n = 1, 2) DINF15 7 DINF7 14 DINF14 6 DINF6 13 DINF13 5 DINF5 12 DINF12 4 DINF4 11 DINF11 3 DINF3 10 DINF10 2 DINF2 9 DINF9 1 DINF1 8 DINF8 0 DINF0 DINFa DINF15 to DINF8 DINF7 to DINF0 CAN bus diagnostic information Number of bits starting from SOF Information from last 8 bits User's Manual U14665EJ4V0UD 471 CHAPTER 18 FCAN CONTROLLER 18.4.27 CANn synchronization control register (CnSYNC) The CnSYNC register controls the data bit time for transmission speed. This register can be read/written in 16-bit units. The C2SYNC register is valid only in models PD703076AY, 703079AY, 703079Y, 70F3079AY, and 70F3079Y. Cautions 1. The CPU is able to read the CnSYNC register at any time. 2. Writing to the CnSYNC register is enabled in initialization mode (when CnCTRL register's INIT bit = 1). 3. The limit values of the CAN protocol when setting the SPTa bit and DBTa bit are as follows (a = 0 to 4). * 5 x BTL SPT (sampling point) 17 x BTL [4 SPT4 to SPT0 set values 16] * 8 x BTL DBT (data bit time) 25 x BTL [7 DBT4 to DBT0 set values 24] * SJW (Synchronization jump width) DBT - SPT * 2 (DBT - SPT) 8 Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) (1/2) After reset: 0218H R/W Addresses: C1SYNC: xxmFFC5EH (m = 3, 7, B) C2SYNC: xxmFFC9EH (m = 3, 7, B) 15 CnSYNC (n = 1, 2) 0 7 SPT2 14 0 6 SPT1 13 0 5 SPT0 12 SAMP 4 DBT4 11 SJW1 3 DBT3 10 SJW0 2 DBT2 9 SPT4 1 DBT1 8 SPT3 0 DBT0 SAMP 0 1 Bit sampling specification Sample data received at the sampling point once Sample received data three times and majority value used as sampled value SJW1 0 0 1 1 SJW0 0 1 0 1 BTL BTL x 2 BTL x 3 BTL x 4 Synchronization jump width Note Note As stipulated in CAN protocol specification Ver. 2.0, Part B active. Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) 472 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (2/2) SPT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SPT3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SPT2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Other than above Sampling point within bit timing is selected. DBT4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DBT3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 DBT2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Other than above 1-bit data length is set for CAN bus DBT1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DBT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BTL x 8 BTL x 9 BTL x 10 BTL x 11 BTL x 12 BTL x 13 BTL x 14 BTL x 15 BTL x 16 BTL x 17 BTL x 18 BTL x 19 BTL x 20 BTL x 21 BTL x 22 BTL x 23 BTL x 24 BTL x 25 Setting prohibited Data bit time SPT1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SPT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Position of sampling point BTL x 3 BTL x 4 BTL x 5 BTL x 6 BTL x 7 BTL x 8 BTL x 9 BTL x 10 BTL x 11 BTL x 12 BTL x 13 BTL x 14 BTL x 15 BTL x 16 BTL x 17 Setting prohibited Note Note Note This setting is reserved for setting sample point extension and is not compliant with the CAN protocol specifications. Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) User's Manual U14665EJ4V0UD 473 CHAPTER 18 FCAN CONTROLLER 18.5 Cautions Regarding Bit Set/Clear Function The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if values are written directly to these registers, so do not directly write values to them (via bit manipulation, read/modify/write, or direct writing of target values). * CAN global status register (CGST) * CAN global interrupt enable register (CGIE) * CANn control register (CnCTRL) * CANn definition register (CnDEF) * CANn interrupt enable register (CnIE) Remark n = 1, 2 All 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 18-3 to set or clear the lower 8 bits in these registers. Setting or clearing the lower 8 bits in the above registers is performed in combination with the higher 8 bits (see Figure 18-4). Figure 18-3 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Figure 18-3. Example of Bit Setting/Clearing Operations Register's current values 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 Write values 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 set 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 clear 1 Bit status Clear Clear No change Clear No change No change Set Set Register's value after write operations 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 474 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-4. 16-Bit Data During Write Operation 15 set 7 14 set 6 13 set 5 12 set 4 11 set 3 10 set 2 9 set 1 8 7 6 5 4 3 2 1 0 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n 0 0 1 1 clear n 0 1 0 1 Status of bit n after bit set/clear operation No change 0 1 No change Remark n = 0 to 7 User's Manual U14665EJ4V0UD 475 CHAPTER 18 FCAN CONTROLLER 18.6 Time Stamp Function Cautions 1. In the PD703075AY, 703076AY, 703078AY, 703079AY, and 70F3079AY, the time stamp function by SOF detection at message transmission/reception cannot be used. Only the time stamp function by EOF detection at message reception can be used for the PD703075AY, 703076AY, 703078AY, 703079AY, and 70F3079AY. However, only the value captured by the M_TIME register is valid when the TSM bit of the CGST register is set to 1 and the TMR bit of the CnCTRL register is set to 1. 2. When two FCAN channels are simultaneously used and the time stamp function using SOF detection at message reception is used in the PD703079Y and 70F3079Y, the following software countermeasures should be taken. * Do not set mask 2 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 100) or mask 3 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 101) as the receive buffer in the receive buffer mask setting. * Prohibit the use of the last message buffer (32th) on software. * Disable the interrupt of the last message buffer (32th). * Do not set three or more transmit request flags (set TRQ bit = 1 and clear TRQ bit = 0 in the SC_STAT00 to SC_STAT31 registers) of FCAN1 or FCAN2 at the same time. The FCAN controller supports a time stamp function. This function is needed to build a global time system. The time stamp function is implemented using a 16-bit free-running time stamp counter. Two types of time stamp functions can be selected for message reception in the FCAN controller. Use bit 3 (TMR) of the CANx control register (CxCTRL) to set the desired time stamp function (x = 1, 2). When the TMR bit is 0, the time stamp counter value is captured after the SOF is detected on the CAN bus (see Figure 18-5) and when the TMR bit is 1, the time stamp counter value is captured after the EOF is detected on the CAN bus (a valid message is confirmed) (see Figure 18-6). 476 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-5. Time Stamp Function Setting for Message Reception (When CxCTRL Register's TMR Bit = 0) SOF ACK field EOF Message CAN message buffer n Time stamp counter <1> Temporary buffer <2> M_TIMEn Figure 18-6. Time Stamp Function Setting for Message Reception (When CxCTRL Register's TMR Bit = 1) SOF ACK field EOF Message CAN message buffer n Time stamp counter <1> M_TIMEn User's Manual U14665EJ4V0UD 477 CHAPTER 18 FCAN CONTROLLER In a global time system, the time value must be captured using the SOF. In addition, the ability to capture the time stamp counter value when message is stored in CAN message buffer n is useful for evaluating the FCAN controller's performance. The captured time stamp counter value is stored in CAN message buffer n, so CAN message buffer n has its own time stamp function (n = 00 to 31). When the SOF is detected on the CAN bus while transmitting a message, there is an option to replace the last two bytes of the message with the captured time stamp counter value by setting bit 5 (ATS) of CAN message control register n (M_CTRLn). This function can be selected for CAN message buffer n on a buffer by buffer basis. Figure 18-7 shows the time stamp setting when the ATS bit = 1. Figure 18-7. Time Stamp Function Setting for Message Transmission (When M_CTRL Register's ATS Bit = 1) SOF ACK field EOF Message <2> Time stamp counter <1> Temporary buffer 478 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Table 18-12. Example When Adding Captured Time Stamp Counter Value to Last 2 Bytes of Transmit Message Data Field Note 1 DLC Bit Value 1 2 3 4 5 6 7 8 9 to 15 Data 1 M_DATAn0 register value Note 2 M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value Data 2 - Note 3 Note 2 M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value Data 3 - - Note 3 Note 2 M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value Data 4 - - - Note 3 Note 2 M_DATAn3 register value M_DATAn3 register value M_DATAn3 register value M_DATAn3 register value Data 5 - - - - Note 3 Note 2 M_DATAn4 register value M_DATAn4 register value M_DATAn4 register value Data 6 - - - - - Note 3 Note 2 M_DATAn5 register value M_DATAn5 register value Data 7 - - - - - - Note 3 Note 2 Note 2 Data 8 - - - - - - - Note 3 Note 3 Notes 1. See 18.4.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31). 2. The lower 8 bits of the time stamp counter value when the SOF is detected on the CAN bus 3. The higher 8 bits of the time stamp counter value when the SOF is detected on the CAN bus Remark n = 00 to 31 User's Manual U14665EJ4V0UD 479 CHAPTER 18 FCAN CONTROLLER 18.7 Message Processing A modular system is used for the FCAN controller. Consequently, messages can be placed at any location within the message area. The messages can be linked to mask functions that are in turn linked to CAN modules. 18.7.1 Message transmission The FCAN system is a multiplexed communication system. system is determined based on message identifiers (IDs). To facilitate communication processing by application software when there are several messages awaiting transmission, the CAN module uses hardware to check the message IDs and automatically determine whether or not linked messages are prioritized. This eliminates the need for software-based priority control. In addition, the priority at transmission can be controlled by setting the PBB bit of the CnDEF register. * When the PBB bit is set to 0 (see Figure 18-8) Transmission priority is controlled by the identifier (ID). The numberNote of messages waiting to be transmitted in the message buffer that can be set simultaneously by application software is up to five messages per CAN module. Note The number of message buffers when the TRQ bit of the M_STAT00 to M_STAT31 registers = 1. * When the PBB bit is set to 1 (see Figure 18-9) Transmission priority is controlled by the message numbers. The number of messages waiting to be transmitted in the message buffer is not limited by the application software. The priority of message transmission within this 480 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-8. Message Processing Example (When PBB Bit = 0) Message No. Message waiting to be transmitted 0 1 2 3 4 5 6 7 8 9 ID = 123H ID = 223H ID = 023H ID = 120H ID = 229H CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3. Message 8 4. Message 5 5. Message 2 Figure 18-9. Message Processing Example (When PBB Bit = 1) Message No. Message waiting to be transmitted 0 1 2 3 4 5 6 7 8 9 ID = 123H ID = 223H ID = 023H ID = 120H ID = 229H CAN module transmits messages in the following sequence. 1. Message 1 2. Message 2 3. Message 5 4. Message 6 5. Message 8 User's Manual U14665EJ4V0UD 481 CHAPTER 18 FCAN CONTROLLER 18.7.2 Message reception When two or more message buffers of the CAN module receive a message, the storage priority of the received messages is as follows (the storage priority differs between data frames and remote frames). Table 18-13. Storage Priority for Data Frame Reception Priority 2 (High) 3 4 5 6 (Low) Unmasked message buffer Message buffer linked to mask 0 Message buffer linked to mask 1 Message buffer linked to mask 2 Message buffer linked to mask 3 Conditions Table 18-14. Storage Priority for Remote Frame Reception Priority 1 (High) 2 3 4 5 6 (Low) Transmit message buffer Unmasked message buffer Message buffer linked to mask 0 Message buffer linked to mask 1 Message buffer linked to mask 2 Message buffer linked to mask 3 Conditions A message (data frame or remote frame) is always stored in a receive message buffer with a higher priority, not in a receive buffer with a lower priority. For example, when the unmasked receive message buffer and the message buffer linked to mask 0 have the same ID, a message is always stored in the unmasked receive message buffer even if the unmasked receive message buffer has already received a message. When two or more message buffers with the same priority exist in the same CAN module, the priority is as follows. Table 18-15. Priority of Same Priority Level Priority 1 (High) 2 (Low) DN bit of M_STAT register is not set (1) DN bit of M_STAT register is set (1) Condition When two or more message buffers with the same priority exist, the message buffer with the smaller message number takes precedence. Also, when two or more message buffers with the same ID exist, the message buffer with the smaller message number takes precedence. 482 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.8 Mask Function A mask linkage function can be defined for each received message. This means that there is no need to distinguish between local masks and global masks. When the mask function is used, the received message's identifier is compared with the message buffer's identifier and the message can be stored in the defined message buffer regardless of whether the mask sets "0" or "1" as a result of the comparison. When the mask function is operating, a bit whose value is defined as "1" by masking is not subject to the abovementioned comparison between the received message's identifier and the message buffer's identifier. However, this comparison is performed for any bit whose value is defined as "0" by masking. For example, let us assume that all messages that have a standard-format ID in which bits ID27 to ID25 = 0 and bits ID24 and ID22 = 1 are to be stored in message buffer 14 (which is linked by CAN module 1 or mask 1 as was explained in 18.4.6). The procedure for this example is shown below. <1> Identifier bits to be stored in message buffer ID28 x ID27 0 ID26 0 ID25 0 ID24 1 ID23 x ID22 1 ID21 x ID20 x ID19 x ID18 x x = don't care Messages with ID in which bits ID27 to ID25 = 0 and bits ID24 and ID22 = 1 are registered (initialized) in message buffer 14 (see 18.4.5). <2> Identifier bits set to message buffer 14 (example) (Using CAN message ID registers L14 and H14 (M_IDL14 and M_IDH14)) ID28 0 ID17 0 ID6 0 ID27 0 ID16 0 ID5 0 ID26 0 ID15 0 ID4 0 ID25 0 ID14 0 ID3 0 ID24 1 ID13 0 ID2 0 ID23 0 ID12 0 ID1 0 ID22 1 ID11 0 ID0 0 ID21 0 ID10 0 ID20 0 ID9 0 ID19 0 ID8 0 ID18 0 ID7 0 Message buffer 14 is set as a standard-format identifier linked to mask 1 (see 18.4.6). User's Manual U14665EJ4V0UD 483 CHAPTER 18 FCAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 1 CMID17 1 CMID6 1 CMID27 0 CMID16 1 CMID5 1 CMID26 0 CMID15 1 CMID4 1 CMID25 0 CMID14 1 CMID3 1 CMID24 0 CMID13 1 CMID2 1 CMID23 1 CMID12 1 CMID1 1 CMID22 0 CMID11 1 CMID0 1 CMID21 1 CMID10 1 CMID20 1 CMID9 1 CMID19 1 CMID8 1 CMID18 1 CMID7 1 1: Do not compare (mask) 0: Compare Values are written to mask 1 (see 18.4.18), bits CMID27 to CMID24 and CMID22 = 0 and bits CMID28, CMID23, and CMID21 to CMID0 = 1. 484 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.9 Protocol FCAN is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. The CAN specification is generally divided into two layers (physical layer and data link layer). In turn, the data link layer includes logical link control and medium access control. The composition of these layers is illustrated in Figure 18-10 below. Figure 18-10. Composition of Layers Higher Application layer Data link layer Not applicable Message and status handling rules * Logical link control (LLC) * Medium access control (MAC) Protocol rules Signal level and bit expression rules Lower Physical layer 18.9.1 Protocol mode function (1) Standard format mode In this mode 2048 different identifiers can be set. The standard format mode uses 11-bit identifiers, which means that it can handle up to 2032 messages. (2) Extended format mode This mode is used to extend the number of identifiers that can be set. * While the standard format mode uses 11-bit identifiers, the extended format mode uses 29-bit (11 bits + 18 bits) identifiers which increases the number of messages that can be handled to 2048 x 218 messages. * Extended format mode is set when "recessive (R): recessive in wired OR" is set for both the SRR and IDE bits in the arbitration field. * When an extended format mode message and a standard format mode remote frame are transmitted at the same time, the node that transmitted the extended format mode message is set to receive mode. User's Manual U14665EJ4V0UD 485 CHAPTER 18 FCAN CONTROLLER 18.9.2 follows. Message formats Four types of frames are used in CAN protocol messages. The output conditions for each type of frame are as * Data frame: * Remote frame: * Error frame: * Overload frame: Remark Frame used for transmit data Frame used for transmit requests from receiving side Frame that is output when an error has been detected Frame that is output when receiving side is not ready Dominant in wired OR Dominant (D): Recessive (R): Recessive in wired OR In the figure shown below, (D) = 0 and (R) = 1. (1) Data frame and remote frame <1> Data frame A data frame is the frame used for transmit data. This frame is composed of seven fields. Figure 18-11. Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) 486 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER <2> Remote frame A remote frame is transmitted when the receiving node issues a transmit request. A remote frame is similar to a data frame, except that the "data field" is deleted and the RTR bit of the "arbitration field" is recessive. Figure 18-12. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remark The data field is not transferred even if the control field's data length code is not "0000B". (2) Description of fields <1> Start of frame (SOF) The start of frame field is a 1-bit dominant (D) field that is located at the start of a data frame or remote frame. Figure 18-13. Start of Frame (SOF) (Interframe space or bus idle) R D Start of frame (Arbitration field) 1 bit * The start of frame field starts when the bus line level changes. * When "dominant (D)" is detected at the sample point, reception continues. * When "recessive (R)" is detected at the sample point, bus idle mode is set. User's Manual U14665EJ4V0UD 487 CHAPTER 18 FCAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame or remote frame, and protocol mode. This field includes an identifier, frame setting (RTR bit), and protocol mode setting bit. Figure 18-14. Arbitration Field (in Standard Format Mode) Arbitration field R D Identifier RTR (Control field) IDE (r1) (1 bit) r0 ID28 * * * * * * * * * * * * * * * * * * * * ID18 (11 bits) (1 bit) Figure 18-15. Arbitration Field (in Extended Format Mode) Arbitration field R D IdentifierNote SRR IDE Identifier RTR (Control field) r1 r0 ID28 * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Note Setting the higher 7 bits of the identifier as 1111111B is prohibited. Cautions 1. ID28 to ID0 are identifier bits. 2. Identifier bits are transferred in MSB-first order. Table 18-16. RTR Frame Settings Frame Type Data frame Remote frame RTR Bit Dominant Recessive Table 18-17. Protocol Mode Setting and Number of Identifier (ID) Bits Protocol Mode Standard format mode Extended format mode SRR Bit None Recessive (R) IDE Bit Dominant (D) Recessive (R) No. of Bits 11 bits 29 bits 488 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER <3> Control field The control field sets "N" as the number of data bytes in the data field (N = 0 to 8). r1 and r0 are fixed as dominant (D). The data length code bits (DLC3 to DLC0) set the byte count. Remark DLC3 to DLC0: Bits 3 to 0 in CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) (See 18.4.1) Figure 18-16. Control Field (Arbitration field) R D RTR r1 (IDE) r0 Control field (Data field) DLC3 DLC2 DLC1 DLC0 In standard format mode, the arbitration field's IDE bit is the same bit as the r1 bit. Table 18-18. Data Length Code Settings Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 8 bytes regardless of the value of DLC3 to DLC0 Data Byte Count Other than above Caution In the remote frame, there is no data field even if the data length code is not 0000B. User's Manual U14665EJ4V0UD 489 CHAPTER 18 FCAN CONTROLLER <4> Data field The data field contains the amount of data set by the control field. Up to 8 units of data can be set. Remark Data units in the data field are each 8 bits long and are ordered MSB first. Figure 18-17. Data Field (Control field) R D Data (8 bits) Data field (CRC field) Data (8 bits) <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. It includes a 15-bit CRC sequence and a 1-bit CRC delimiter. Figure 18-18. CRC Field (Data field, control field) R D CRC field (ACK field) CRC sequence CRC delimiter (1 bit) (15 bits) * The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as: X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 * Transmitting node: No bit stuffing in start of frame, arbitration field, control field, or data field: the * Receiving node: transferred CRC sequence is calculated entirely from basic data bits. The CRC sequence calculated using data bits that exclude the stuffing bits in the receive data is compared with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node is passed to an error frame. 490 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER <6> ACK field The ACK field is used to confirm normal reception. It includes a 1-bit ACK slot and a 1-bit ACK delimiter. Figure 18-19. ACK Field (CRC field) R D ACK field (End of frame) ACK slot (1 bit) ACK delimiter (1 bit) * The receiving node outputs the following depending on whether or not an error is detected between the start of frame field and the CRC field. If an error is detected: ACK slot = Recessive (R) If no error is detected: ACK slot = Dominant (D) * The transmitting node outputs two "recessive(R)" bits and confirms the receiving node's receive status. <7> End of frame (EOF) The end of frame field indicates the end of transmission or reception. It includes 7 "recessive(R)" bits. Figure 18-20. End of Frame (EOF) (Ack field) R D End of frame (Interframe space or overload frame) (7 bits) User's Manual U14665EJ4V0UD 491 CHAPTER 18 FCAN CONTROLLER <8> Interframe space The interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next one. * Error active node When the bus is idle, transmit enable mode is set for each node. Transmission then starts from a node that has received a transmit request. If the node is an error active node, the interframe space is composed of a 3- or 2-bit intermission field and bus idle field. * Error passive node After an 8-bit bus idle field, transmit enable mode is set. Receive mode is set if a transmission starts from a different node during bus idle mode. The error passive node is composed of an intermission field, suspend transmission field, and bus idle field. Figure 18-21. Interframe Space (a) Error active (Frame) R D Intermission (3 or 2 bits) Bus idle (0 or more bits) Interframe space (Frame) (b) Error passive (Frame) R D Interframe space (Frame) Intermission (3 or 2 bits) Suspend transmission (8 bits) Bus idle (0 or more bits) * Bit length of intermission When transmission is pending, transmission is resumed after a 3-bit intermission. When receiving, the receive operation starts after only two bits. * Bus idle This mode is set when no nodes are using any buses. * Suspend transmission This is an 8-bit recessive (R) field that is transmitted from a node that is in error passive mode. 492 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Table 18-19. Operation When Third Bit of Intermission Is "Dominant (D)" Transmit Status No pending transmissions Operation A receive operation is performed when start of frame output by other node is detected. Pending transmission exists The identifier is transmitted when start of frame output by local node is detected. <9> Error frame An error frame is used to output from a node in which an error has been detected. When a passive error flag is being output, if there is "dominant (D)" output from another node, the passive error flag does not end until 6 consecutive bits are detected on the same level. If the bit following the 6 consecutive "recessive (R)" bits is "dominant (D)", the error frame ends when the next "recessive (R)" bit is detected. Figure 18-22. Error Frame Error frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Error delimiter Error flag Error flag Error bit (<5>) No <1> Error flag Name Bit count 6 Error active node Definition Consecutive output of 6 "dominant (D)" bits Error passive node Consecutive output of 6 "recessive (R)" bits <2> Error flag 0 to 6 A node that receives an error flag is a node in which bit stuffing errors are detected, after which an error flag is output. <3> Error delimiter 8 8 consecutive "recessive (R)" bits are output. If a "dominant (D)" bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> Error bit - This bit is output following the bit where an error occurred. If the error is a CRC error, it is output following an ACK delimiter. <5> Interframe space or overload frame 3/10 20 MAX. An interframe space or overload frame starts from here. User's Manual U14665EJ4V0UD 493 CHAPTER 18 FCAN CONTROLLER <10> Overload frame An overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. If a bit error is detected during intermission mode, it is output starting from the bit following the bit where the bit error was detected. Figure 18-23. Overload Frame Overload frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Overload delimiter Overload flag (node n) Overload flag (node m) Frame (<5>) No <1> Name Overload flag starting from node m Bit count 6 Definition Consecutive output of 6 "dominant (D)" bits. Output when node m is not ready to receive. <2> Overload flag starting from node n 0 to 6 Node n, which has received an overload flag in the interframe space, outputs an overload flag <3> Overload delimiter 8 8 consecutive "recessive (R)" bits are output. If a "dominant (D)" bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> Frame - Output following an end of frame, error delimiter, or overload delimiter. <5> Interframe space or overload frame 3/10 20 MAX. An interframe space or overload frame starts from here. Remark nm 494 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.10 Functions 18.10.1 Determination of bus priority (1) When one node has starting transmitting * In bus idle mode, the node that outputs data first starts transmitting. (2) When several nodes have started transmitting * The node that has the longest string of consecutive "dominant (D)" bits starting from the first bit in the arbitration field has top priority for bus access ("dominant (D)" bits take precedence due to wired OR bus arbitration). * The transmitting node compares the arbitration field which it has output and the bus data level Table 18-20. Determination of Bus Priority Matched levels Mismatched levels Transmission continues When a mismatch is detected, data output stops at the next bit, and the operation switches to reception. (3) Priority between data frame and remote frame * If a bus conflict occurs between a data frame and a remote frame, the data frame takes priority because its last bit (RTR) is "dominant (D)". 18.10.2 Bit stuffing Bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for at least five consecutive bits. Table 18-21. Bit Stuffing Transmit When transmitting data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and CRC fields, one bit of data whose level is inverted from the previous level is inserted before the next bit. Receive When receiving data frames and remote frames, if the same level is maintained for at least five bits between the start of frame and CRC fields, the next bit of data is deleted before reception is resumed. 18.10.3 Multiple masters Since bus priority is determined based on the identifier, any node can be used as the bus master. 18.10.4 Multi-cast Even when there is only one transmitting node, the same identifier can be set for several nodes, so that the same data can be received by several nodes at the same time. User's Manual U14665EJ4V0UD 495 CHAPTER 18 FCAN CONTROLLER 18.10.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function can be used to set the FCAN controller to sleep (standby) mode to reduce power consumption. The CAN sleep mode is set via the procedure stipulated in the CAN specifications. The CAN sleep mode can be set to wake up by the bus operation, however the CAN stop mode cannot be set to wake up by bus operation (this is controlled via CPU access). 18.10.6 Error control function (1) Types of errors Table 18-22. Types of Errors Error Type Description of Error Detection Method Detection Condition Transmit/ Receive Bit error Comparison of output level and bus level (excludes stuff bits) Stuff error Use stuff bits to check receive data Six consecutive bits of same-level data Mismatch between levels Transmitting/ receiving nodes Transmitting/ receiving nodes CRC error Comparison of CRC generated from receive data and received CRC sequence Form error Check fixed-format field/frame Detection of inverted fixed format Receiving node * CRC delimiter * ACK field * End of frame * Error frame * Overload frame ACK error Use transmitting node to check ACK slot Use ACK slot to detect recessive Transmitting node ACK slot CRC mismatch Receiving node Start of frame to data field Bits outputting data on bus in start of frame to end of frame, error frame, or overload frame Start of frame to CRC sequence Detected Status Field/Frame (2) Error frame output timing Table 18-23. Error Frame Output Timing Error Type Bit error, stuff error, form error, ACK error CRC error Error frame is output at the next bit following the ACK delimiter Output Timing Error frame is output at the next bit following the bit where error was detected (3) Handling of errors The transmitting node retransmits the data frame or remote frame after the error frame has been transmitted. 496 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (4) Error statuses (a) Types of error statuses The three types of error statuses are listed below. Error active Error passive Bus off * The error status is controlled by the transmit error counter and receive error counter (see 18.4.22 CANn error count register (CnERC)). * The various error statuses are categorized according to their error counter values. * The error flags used for error statuses differ between transmit and receive operations. * When the error counter value reaches 96 or more, the bus status must be tested since the bus may become seriously damaged. * During start-up, if only one node is active, the error frame and data are repeatedly re-sent because no ACK is returned even data has been transmitted. In such cases, bus off mode cannot be set. Even if the transmitting node that is sending the transmit message repeatedly experiences an error status, bus off mode cannot be set. Table 18-24. Types of Error Statuses Error Status Type Error active Operation Transmit/ receive Error passive Transmit Receive Bus off Transmit 128 to 255 128 or more 256 or more Error Counter Value 0 to 127 Type of Output Error Flag Active error flag (6 consecutive "dominant (D)" bits) Passive error flag (6 consecutive "recessive (R)" bits) Transfer is not possible. When a string of at least 11 consecutive "recessive (R)" bits occurs 128 times, the error counter is zero-cleared and error active status can be resumed. User's Manual U14665EJ4V0UD 497 CHAPTER 18 FCAN CONTROLLER (b) Error counter The error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. The count up/count down timing occurs at the first bit of the error delimiter. Table 18-25. Error Counter Status Transmit Error Counter (TEC7 to TEC0) When receiving node has detected an error (except for bit errors that occur in an active error flag or overload flag) When "dominant (D)" is detected following error frame's overload flag output by the receiving node When transmitting node has sent an error flag [When error counter = 0] <1> When an ACK error was detected in error passive status and a "dominant (D)" was not detected during error flag output <2> When a stuff error occurs in the arbitration field Detection of bit error during output of active error flag or overload flag (transmitting node with error active status) Detection of bit error during output of active error flag or overload flag (receiving node with error active status) When 14 consecutive "dominant (D)" bits were detected from the start of each node's active error flag or overload flag, followed by detection of eight consecutive dominant bits. Each node has detected eight consecutive dominant bits after a passive error flag. The transmitting node has completed a transmit operation without any errors (0 if error counter value is 0). The receiving node has completed a receive operation without any errors. No change * -1 (1 REC7 to REC0 127) * 0 (REC7 to REC0 = 0) * 127 is set (REC7 to REC0 > 127) -1 No change +8 +8 No change +8 +8 No change +8 No change No change +8 No change +1 Receive Error Counter (REC7 to REC0) (c) Occurrence of bit error during intermission In this case, an overload frame occurs. Caution When an error occurs, error control is performed according to the contents of the transmitting and receiving error counters as they existed prior to the error's occurrence. The error counter value is incremented only after an error flag has been output. 498 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.10.7 Baud rate control function (1) Prescaler The FCAN controller of the V850/SF1 includes a prescaler for dividing the clock supplied to the CAN (fMEM1). This prescaler generates a clock (fBTL) that is based on a division ratio ranging from 2 to 128 applied to the CAN base clock (fMEM) when the CnBRP register's TLM bit = 0, and from 2 to 256 when the TLM bit = 1 (see 18.4.25 CANn bit rate prescaler register (CnBRP)). (2) Nominal bit time (8 to 25 time quantum) The definition of 1 data bit time is shown below. Remark 1 time quantum = 1/fBTL Figure 18-24. Nominal Bit Time Nominal bit time Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point SJW Segment name Sync segment (Synchronization Segment) Prop segment (Propagation Segment) 1 Segment length Description This segment begins when resynchronization occurs. 1 to 8 (programmable) This segment is used to absorb the delays caused by the output buffer, CAN bus, and input buffer. It is set to return an ACK signal until phase segment 1 begins. Prop segment time (output buffer delay) + (CAN bus delay) + (input buffer delay) Phase segment 1 (Phase Buffer Segment 1) Phase segment 2 (Phase Buffer Segment 2) 1 to 8 (programmable) This segment is used to compensate for errors in the data bit time. It accommodates a wide margin or error but slows down communication speed. Maximum value from phase segment 1 or IPT Note (IPT = 0 to 2) This sets the range for bit synchronization. SJW (reSynchronization Jump Width) 1 to 4 (programmable) Note IPT: Information Processing Time IPT is a period in which the current bit level is referenced and judgement for the next processing is performed. IPT is indicated by the expression below using the clock supplied to CAN (fMEM1). IPT = 1/fMEM1 x 3 User's Manual U14665EJ4V0UD 499 CHAPTER 18 FCAN CONTROLLER (3) Data bit synchronization * Since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. * As for the transmitting node, data is transmitted in sync with the transmitting node's bit timing. (a) Hardware synchronization This is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode. * When a falling edge is detected on the bus, the current bit is assigned to the sync segment and the next bit is assigned to the prop segment. In such cases, synchronization is performed regardless of the SJW. * Since bit synchronization must be established after a reset or after a wakeup, hardware synchronization is performed only at the first level change that occurs on the bus (for the second and subsequent level changes, bit synchronization is performed as shown below). Figure 18-25. Coordination of Data Bit Synchronization Bus idle CAN bus Start of frame Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 500 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (b) Resynchronization Resynchronization is performed when a level change is detected on the bus (only when the previous sampling is at the recessive level) during a receive operation. * The edge's phase error is produced by the relative positions of the detected edge and sync segment. Negative: Edge is after sample point (phase error) * When the edge is detected as within the bit timing specified by the SJW, synchronization is performed in the same way as hardware synchronization. * When the edge is detected as extending beyond the bit timing specified by the SJW, synchronization is performed on the following basis. When phase error is positive: Phase segment 1 is lengthened to equal the SJW When phase error is negative: Phase segment 2 is shortened to equal the SJW * A "shifting" of the baud rate for the transmitting and receiving nodes moves the relative position of the sample point for data on the receiving node. Figure 18-26. Resynchronization Previous bit CAN bus SOF Bit timing Sync segment SJW Prop segment Next bit Phase segment 1 Phase segment 2 User's Manual U14665EJ4V0UD 501 CHAPTER 18 FCAN CONTROLLER 18.11 Operations 18.11.1 Initialization processing Figure 18-27 shows a flowchart of initialization processing. The register setting flow is shown in Figures 18-28 to 18-40. Figure 18-27. Initialization Processing START CSTP = 1? (CSTOP) No Set CAN main clock selection register (CGCS) Yes CSTP = 0 (CSTOP) : See setting shown in Figure 18-28 Setting of CAN Main Clock Select Register (CGCS) Set CAN global interrupt enable register (CGIE) : See setting shown in Figure 18-29 Setting of CAN Global Interrupt Enable Register (CGIE) Set CAN global status register (CGST) set INIT = 1 (CnCTRL) : See setting shown in Figure 18-30 Setting of CAN Global Status Register (CGST) ISTAT = 1? (CnCTRL) Yes Set CANn bit rate prescaler (CnBRP) No : See setting shown in Figure 18-31 Setting of CANn Bit Rate Prescaler (CnBRP) Set CANn synchronization control register (CnSYNC) : See setting shown in Figure 18-32 Setting of CANn Synchronization Control Register (CnSYNC) Set CANn interrupt enable register (CnIE) Set CANn definition register (CnDEF) Set CANn control register (CnCTRL) : See setting shown in Figure 18-33 Setting of CANn Interrupt Enable Register (CnIE) : See setting shown in Figure 18-34 Setting of CANn Definition Register (CnDEF) : See setting shown in Figure 18-35 Setting of CANn Control Register (CnCTRL) Mask required for message ID? Yes No Set mask (CnMASKa) : See Figure 18-36 Setting of CANn Address Mask a Registers L and H (CnMASKLa and CnMASKHa) Set message buffer (repeat as many times as number of messages) clear INIT = 1 (CnCTRL) : See Figure 18-37 Message Buffer Setting ISTAT = 0? (CnCTRL) Yes END No Remark a = 0 to 3 n = 1, 2 502 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-28. Setting of CAN Main Clock Select Register (CGCS) START Select clock for memory access controller (MCP0 to MCP3) fMEM Select global timer clock (GTCS0, GTCS1) fGTS1 Select system timer prescaler (CGTS0 to CGTS7) fGTS fMEM = fMEM1/ (n + 1) n = 0 to 15 (set using bits MCP0 to MCP3) GTCS1, GTCS0 = 00: fGTS1 = fMEM/2 GTCS1, GTCS0 = 01: fGTS1 = fMEM/4 GTCS1, GTCS0 = 10: fGTS1 = fMEM/8 GTCS1, GTCS0 = 11: fGTS1 = fMEM/16 fGTS = fGTS1/ (n + 1) n = 0 to 255 (set using bits CGTS0 to CGTS7) Remark fMEM = CAN base clock fMEM1 = fXX: Clock supplied to CAN fGTS1 = Global timer clock fGTS = System timer prescaler Figure 18-29. Setting of CAN Global Interrupt Enable Register (CGIE) START * Interrupt occurs if memory address in undefined area is accessed. * Interrupt occurs if the GOM bit is not cleared (0) under the following conditions. * When shutdown is disabled (EFSD bit = 0). * When a CAN module not in the initialization status (ISTAT bit = 0) exists. * Interrupt occurs if invalid write operation is performed when the GOM bit = 1, such as in TEMP buffer. * Interrupt occurs if CAN module register (with name starting with "Cn" (n = 1, 2)) is accessed when the GOM bit = 0. Enable interrupt for G_IE1 bit No Yes set G_IE1 = 1 clear G_IE1 = 0 Enable interrupt for G_IE2 bit No Yes set G_IE2 = 1 clear G_IE2 = 0 Remark GOM: Bit of CAN global status register (CGST) EFSD: Bit of CAN global status register (CGST) ISTAT: Bit of CANn control register (CnCTRL) User's Manual U14665EJ4V0UD 503 CHAPTER 18 FCAN CONTROLLER Figure 18-30. Setting of CAN Global Status Register (CGST) START Start FCAN operation set GOM = 1 clear GOM = 0 Use time stamp function? No Yes set TSM = 1 clear TSM = 0 Figure 18-31. Setting of CANn Bit Rate Prescaler Register (CnBRP) START Transfer speed is 125 kbps or less Yes BTYPE = 0 (low speed) No BTYPE = 1 (high speed) fBTL setting When TLM = 0 BRP5 to BRP0 When TLM = 1 BRP7 to BRP0 When TLM = 0 fBTL = fMEM/{(m + 1) x 2} m = 0 to 63 (set using bits BRP5 to BRP0) When TLM = 1 fBTL = fMEM/(m + 1) m = 0 to 255 (set using bits BRP7 to BRP0) fBTL Remarks 1. fBTL = CAN protocol layer base system clock fMEM = CAN base clock 2. n = 1, 2 504 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-32. Setting of CANn Synchronization Control Register (CnSYNC) START Set data bit time (DBT4 to DBT0) 1 bit time = BTL x (m + 1) m = 7 to 24 (set using bits DBT4 to DBT0) Set sampling point (SPT4 to SPT0) Sampling point = BTL x (m + 1) m = 2 to 16 (set using bits SPT4 to SPT0)Note Set SJW (SJW1, SJW0) SJW = BTL x (m + 1) m = 0 to 3 (set using bits SJW1 and SJW0) Set once-only (single shot) sampling Yes SAMP = 0 Set sampling for one location only No SAMP = 1 Set sampling for three locations Note The setting of m = 2, 3 is reserved for setting sample point extension, and is not compliant with the CAN protocol specifications. Remarks 1. BTL = 1/fBTL (fBTL = CAN protocol layer base system clock) 2. n = 1, 2 User's Manual U14665EJ4V0UD 505 CHAPTER 18 FCAN CONTROLLER Figure 18-33. Setting of CANn Interrupt Enable Register (CnIE) START Interrupt enable flag for end of transmission Enable interrupt for E_INT0? No clear E_INT0 = 1 set E_INT0 = 0 Yes set E_INT0 = 1 clear E_INT0 = 0 Interrupt enable flag for end of reception Enable interrupt for E_INT1? No clear E_INT1 = 1 set E_INT1 = 0 Yes set E_INT1 = 1 clear E_INT1 = 0 Interrupt enable flag for error passive or bus off by TEC Enable interrupt for E_INT2? No clear E_INT2 = 1 set E_INT2 = 0 Yes set E_INT2 = 1 clear E_INT2 = 0 Interrupt enable flag for error passive by REC Enable interrupt for E_INT3? No clear E_INT3 = 1 set E_INT3 = 0 Yes set E_INT3 = 1 clear E_INT3 = 0 Interrupt enable flag for wakeup from CAN sleep mode Enable interrupt for E_INT4? No clear E_INT4 = 1 set E_INT4 = 0 Yes set E_INT4 = 1 clear E_INT4 = 0 Interrupt enable flag for CAN bus error Enable interrupt for E_INT5? No clear E_INT5 = 1 set E_INT5 = 0 Yes set E_INT5 = 1 clear E_INT5 = 0 Interrupt enable flag for CAN error Enable interrupt for E_INT6? No clear E_INT6 = 1 set E_INT6 = 0 Yes set E_INT6 = 1 clear E_INT6 = 0 Remark n = 1, 2 User's Manual U14665EJ4V0UD 506 CHAPTER 18 FCAN CONTROLLER Figure 18-34. Setting of CANn Definition Register (CnDEF) START Set to diagnostic processing mode? No clear MOM = 1 set MOM = 0 Yes Normal operating mode set MOM = 1 clear MOM = 0 Diagnostic processing mode Store to buffer used for diagnostic processing modeNote? No set DGM = 1 clear DGM = 0 Yes clear DGM = 1 set DGM = 0 Determine transmit priority based on identifiers? Transmit priority is determined based on message numbers No set PBB = 1 clear PBB = 0 Yes clear PBB = 1 set PBB = 0 Transmit priority is determined based on identifiers Set single-shot mode? No clear SSHT = 1 set SSHT = 0 Yes Normal operation mode set SSHT = 1 clear SSHT = 0 Single-shot mode: Transmit only once. Do not retransmit. Note Bits 5 to 3 (MT2 to MT0) in CAN message configuration register m (M_CONFm) are set to "111" Remark n = 1, 2 m = 00 to 31 User's Manual U14665EJ4V0UD 507 CHAPTER 18 FCAN CONTROLLER Figure 18-35. Setting of CANn Control Register (CnCTRL) (1/2) (a) PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY START Set time stamp for receiving Store timer value at EOF? Yes set TMR = 1 clear TMR = 0 No clear TMR = 1 set TMR = 0 Set overwrite for receive message buffer Store message of DN flag? Yes clear OVM = 1 set OVM = 0 No set OVM = 1 clear OVM = 0 Do not overwrite message in DN flag (delete new message) Set dominant level for transmit pins Set dominant level to low level? Yes clear DLEVT = 1 set DLEVT = 0 No set DLEVT = 1 clear DLEVT = 0 Set dominant level to high level Set dominant level for receive pins Set dominant level to low level? Yes clear DLEVR = 1 set DLEVR = 0 No set DLEVR = 1 clear DLEVR = 0 Set dominant level to high level Remark n = 1, 2 508 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-35. Setting of CANn Control Register (CnCTRL) (2/2) (b) PD703078Y, 703079Y, 70F3079Y START Set time stamp for receiving Store timer value at SOF?Note Yes clear TMR = 1 set TMR = 0 No set TMR = 1 clear TMR = 0 Store timer value at EOF Set overwrite for receive message buffer Store message of DN flag? Yes clear OVM = 1 set OVM = 0 No set OVM = 1 clear OVM = 0 Do not overwrite message in DN flag (delete new message) Set dominant level for transmit pins Set dominant level to low level? Yes clear DLEVT = 1 set DLEVT = 0 No set DLEVT = 1 clear DLEVT = 0 Set dominant level to high level Set dominant level for receive pins Set dominant level to low level? Yes clear DLEVR = 1 set DLEVR = 0 No set DLEVR = 1 clear DLEVR = 0 Set dominant level to high level Note When two FCAN channels are simultaneously used and the time stamp function using SOF detection at message reception is used in the PD703079Y and 70F3079Y, the following software countermeasures should be taken. * Do not set mask 2 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 100) or mask 3 (MT2 to MT0 bits of the M_CONF00 to M_CONF31 registers = 101) as the receive buffer in the receive buffer mask setting. * Prohibit the use of the last message buffer (32th) on software. * Disable the interrupt of the last message buffer (32th). * Do not set three or more transmit request flags (set TRQ bit = 1 and clear TRQ bit = 0 in the SC_STAT00 to SC_STAT31 registers) of FCAN1 or FCAN2 at the same time. Remark n = 1, 2 User's Manual U14665EJ4V0UD 509 CHAPTER 18 FCAN CONTROLLER Figure 18-36. Setting of CANn Address Mask a Registers L and H (CnMASKLa and CnMASKHa) START Standard frame Yes (y = 0 to 17) Mask setting for standard frame (x = 18 to 28) CMIDy = 1 No Mask setting for extended frame (x = 0 to 28) No Mask ID bit? Yes Mask ID bit? Yes CMIDx = 1 CMIDx = 0 CMIDx = 1 No Mask setting for message ID format CMIDx = 0 Check ID type? Yes CMIDE = 0 No CMIDE = 1 510 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-37. Message Buffer Setting START Set message ID type No Standard frame? Yes IDE = 0 (standard) (M_IDHm) IDE = 1 (extended) (M_IDHm) Set identifier (standard, extended) Set message configuration See Figure 18-38 Setting of CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Set message length Set message control byte See Figure 18-39 Setting of CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Set message status See Figure 18-40 Setting of CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Remark m = 00 to 31 User's Manual U14665EJ4V0UD 511 CHAPTER 18 FCAN CONTROLLER Figure 18-38. Setting of CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) START Release CAN message buffer Yes Use message buffer? No MA2 to MA0 = 000 Message buffer address specification CAN module2 MA2 to MA0 = 010 MA2 to MA0 = 001 CAN module1 Yes Transmit message No Receive message (no mask setting) No Yes MT2 to MT0 = 010 Yes MT2 to MT0 = 001 MT2 to MT0 = 000 Receive message (set mask 0) No Receive message (set mask 1) No Yes MT2 to MT0 = 011 Receive message (set mask 2) No Receive message (set mask 3) No MT2 to MT0 = 111 (used in diagnostic processing mode) Yes MT2 to MT0 = 100 Yes MT2 to MT0 = 101 512 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-39. Setting of CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) START Transmit/receive data frame? Yes RTR = 0 No RTR = 1 Transmit/receive remote frame No Disable interrupt? Yes IE = 0 IE = 1 Enable interrupt Set remote frame auto acknowledge function Remote frame auto acknowledge? Yes RMDE0 = 1 No RMDE0 = 0 Set DN flag when remote frame is received No Set DN flag? Yes RMDE1 = 1 RMDE1 = 0 Apply time stamp? Yes ATS = 1 No ATS = 0 User's Manual U14665EJ4V0UD 513 CHAPTER 18 FCAN CONTROLLER Figure 18-40. Setting of CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) START Clear DN flag clear DN = 1, set DN = 0 (SC_STATm) Clear TRQ flag clear TRQ = 1, set TRQ = 0 (SC_STATm) Clear RDY flag clear RDY = 1, set RDY = 0 (SC_STATm) Remark m = 00 to 31 514 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.11.2 Transmit setting Transmit messages are output from the target message buffer. Figure 18-41. Transmit Setting START Select transmit message buffer Set data (M_DATAmn) Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATm) Set transmit request flag set TRQ = 1, clear TRQ = 0 (SC_STATm) End of transmit operation Remark n = 0 to 7 m = 00 to 31 User's Manual U14665EJ4V0UD 515 CHAPTER 18 FCAN CONTROLLER 18.11.3 Receive setting Receive messages are retrieved from the target message buffer. Figure 18-42. Setting of Receive Completion Interrupt and Reception Operation Using Reception Polling START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Receive completion interrupt occurs Detect target message buffer : Detection methods <1> Detect using CANn information register (CnLAST) <2> Detect using CAN message search start/result register (CGMSS/CGMSR) (see Figure 18-43 Setting of CAN Message Search Start/Result Register (CGMSS/CGMSR)) Clear DN flag clear DN = 1, set DN = 0 (SC_STATm) Receive remote frame No Receive data frame? Receive data frame Yes Transmit operation Get data length Get data Get time stamp No DN = 0 (M_STATm) Yes End of receive operation Remark m = 00 to 31 516 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-43. Setting of CAN Message Search Start/Result Register (CGMSS/CGMSR) START Check DN flag (CDN = 1) Check masked messages? Yes Search non masklinked messages only CMSK = 1 (CGMSS) No CMSK = 0 (CGMSS) Search all messages (regardless of mask setting) No Check message ID? Yes Search standard ID only CIDE = 1 (CGMSS) CIDE = 0 (CGMSS) Do not check message ID format Set start position and start search Get search results User's Manual U14665EJ4V0UD 517 CHAPTER 18 FCAN CONTROLLER 18.11.4 CAN sleep mode In CAN sleep mode, the FCAN controller can be set to standby mode. A wakeup occurs when there is a bus operation. Figure 18-44. CAN Sleep Mode Setting START set SLEEP = 1 clear SLEEP = 0 (CnCTRL) No SLEEP = 1 (CnCTRL) Yes End of CAN sleep mode setting Remark n = 1, 2 Figure 18-45. Clearing of CAN Sleep Mode by CAN Bus Active Status START CAN bus active SLEEP = 0 (CnCTRL) WAKE = 1 (CnDEF) Wakeup interrupt occurs End of CAN sleep mode clearing operation Remark n = 1, 2 518 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER Figure 18-46. Clearing of CAN Sleep Mode by CPU START clear SLEEP = 1 set SLEEP = 0 (CnCTRL) SLEEP = 0 (CnCTRL) End of CAN sleep mode clearing operation Remark n = 1, 2 User's Manual U14665EJ4V0UD 519 CHAPTER 18 FCAN CONTROLLER 18.11.5 CAN stop mode In CAN stop mode, the FCAN controller can be set to standby mode. No wakeup occurs when there is a bus operation (stop mode is controlled by CPU access only). Figure 18-47. CAN Stop Mode Setting START SLEEP = 1 (CnCTRL) Yes set STOP = 1 clear STOP = 0 (CnCTRL) No Set CAN sleep mode (see Figure 18-44) STOP = 1 (CnCTRL) Yes End of CAN stop mode setting No Remark n = 1, 2 Figure 18-48. Clearing of CAN Stop Mode START clear STOP = 1 set STOP = 0 clear SLEEP = 1 set SLEEP = 0 (CnCTRL) STOP = 0 SLEEP = 0 (CnCTRL) End of CAN stop mode clearing operation 520 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.12 Rules for Correct Setting of Baud Rate The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that settings are within the range of limit values. (a) 5 x BTL SPT (sampling point) 17 x BTL [4 SPT4 to SPT0 set values 16] (b) 8 x BTL DBT (data bit time) 25 x BTL [7 DBT4 to DBT0 set values 24] (c) SJW (Synchronization Jump Width) DBT - SPT (d) 2 (DBT - SPT) 8 Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) SPT4 to SPT0 (bits 9 to 5 of CANn synchronization control register (CnSYNC)) DBT4 to DBT0 (bits 4 to 0 of CANn synchronization control register (CnSYNC)) (1) Example of FCAN baud rate setting (when CnBRP register's TLM bit = 0) The following is an example of how correct settings for the CnBRP register and CnSYNC register can be calculated. Conditions from CAN bus: <1> CAN base clock frequency (fMEM): 16 MHz <2> CAN bus baud rate: <3> Sampling point: <4> SJW: 83 kbps 80% or more 3 BTL First, calculate the ratio between the CAN base clock frequency and the CAN bus baud rate frequency as shown below. fMEM / CAN bus baud rate = 16 MHz / 83 kHz 192.77 26 x 3 Set an even number between 2 and 128 to the CnBRP register's bits BRP5 to BRP0 as the setting for the prescaler (CAN protocol layer base system clock: fBTL), then set a value between 8 and 25 to the CnSYNC register's bits DBT4 to DBT0 as the data bit time. Since it is assumed that the SJW value is 3, the maximum setting value for SPT (sampling point) is 3 less than the data bit time setting and is 17 or less. (SPT DBT - 3 and SPT 17) User's Manual U14665EJ4V0UD 521 CHAPTER 18 FCAN CONTROLLER Given the above limit values, the following 4 settings are possible. Prescaler 24 16 12 8 DBT 8 12 16 24 SPT (MAX.) 5 9 13 17 Calculated SPT 5/8 = 62.5% 9/12 = 75% 13/16 = 81% 17/24 = 71% 16 MHz/83 kbps 192 = 64 x 3 = 48 x 4 = 32 x 6 = 24 x 8 = 16 x 12 = 12 x 16 = 8 x 24 = 6 x 32 = 4 x 48 = 3 x 64 <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> The settings that can actually be made for the V850/SF1 are in the range from <4> to <7> above (the section enclosed in broken lines). Among these options in the range from <4> to <7> above, option <6> is the ideal setting for used when actually setting the register. (i) Prescaler (CAN protocol layer base system clock: fBTL) setting fBTL is calculated as below. * fBTL = fMEM/{(a + 1) x 2} : [0 a 63] Value a is set using bits 5 to 0 (BRP5 to BRP0) of the CnBRP register. fBTL = 16 MHz/12 = 16 MHz/{(5 + 1) x 2} thus a = 5 Therefore, CnBRP register = 0005H 522 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER (ii) DBT (data bit time) setting DBT is calculated as below. * DBT = BTL x (a + 1) : [7 a 24] Value a is set using bits 4 to 0 (DBT4 to DBT0) of the CnSYNC register. DBT = BTL x 16 = BTL x (a + 1) thus a = 15 Therefore, CnBRP register's bits DBT4 to DBT0 = 01111B Note that 1/DBT = fBTL/16 1333 kHz/16 83 kbps (nearly equal to the CAN bus baud rate) (iii) SPT (sampling point) setting Given SJW = 3: SJW DBT - SPT 3 16 - SPT SPT 13 Therefore, SPT is set as 13 (max.) SPT is calculated as below. * SPT = BTL x (a + 1) : [4 a 16] Value a is set using bits 9 to 5 (SPT4 to SPT0) of the CnSYNC register. SPT = BTL x 13 = BTL x (12 + 1) thus a = 12 Therefore, the SPT4 to SPT0 bits of the CnSYNC register = 01100B (iv) SJW (Synchronization Jump Width) setting SJW is calculated as below. * SJW = BTL x (a + 1) : [0 a 3] Value a is set using bits11 and 10 (SJW1, SJW0) of the CnSYNC register. CnSYNC register's bits SJW1 and SJW0 = BTL x 3 = BTL x (2 + 1) thus a = 2 Therefore, the SJW1 and SJW0 bits of the CnSYNC register = 10B. The CnSYNC register settings based on these results are shown in Figure 18-49 below. User's Manual U14665EJ4V0UD 523 CHAPTER 18 FCAN CONTROLLER Figure 18-49. CnSYNC Register Settings 15 CnSYNC Setting 0 0 14 0 0 13 0 0 12 SAMP 0 11 SJW1 1 10 SJW0 0 9 SPT4 0 8 SPT3 1 7 SPT2 Setting 1 6 SPT1 0 5 SPT0 0 4 DBT4 0 3 DBT3 1 2 DBT2 1 1 DBT1 1 0 DBT0 1 524 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.13 Ensuring Data Consistency When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent. Two methods are used to ensure data consistency: sequential data read and burst read mode. 18.13.1 Sequential data read When the CPU performs sequential access of a message buffer, data is read from the buffer in the order shown in Figure 18-50 below. Only the FCAN internal operation can set the M_STATn register's DN bit (1) and only the CPU can clear it (0), so during the read operation the CPU must be able to check whether or not any new data has been stored in the message buffer. Figure 18-50. Sequential Data Read Read CPU Clear DN flag clear DN = 1, set DN = 0 (SC_STATn) Read data from message buffer DN = 0 (M_STATn) Yes No End of CPU's read operation Remark n = 00 to 31 User's Manual U14665EJ4V0UD 525 CHAPTER 18 FCAN CONTROLLER 18.13.2 Burst read mode Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the synchrony of data. Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied from the message buffer area to a temporary read buffer. Data continues to be read from the temporary buffer as long as the CPU keeps directly incrementing (+1) the read address (in other words, when data is read in the following order: M_DLCn register M_CTRLn register M_TIMEn register M_DATAn0 to M_DATAn7 registers M_IDLn, M_IDHn register). If these linear address rules are not followed or if access is attempted to an address that is lower than the M_IDHn register's address (such as the M_CONFn register or M_STATn register), burst read mode becomes invalid. Cautions 1. 16-bit read access is required for the entire message buffer area when using the burst read mode. If 8-bit access (byte read operation) is attempted, burst read mode does not start up even if the address is linearly incremented (+1) as described above. 2. Be sure to read out the value of FCAN control registers other than the M_DLCn register before starting the burst read mode. Remark n = 00 to 31 526 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.14 Interrupt Conditions 18.14.1 Interrupts that occur for FCAN controller When interrupts are enabled (condition <1>: the M_CTRLm register's IE bit = 1, conditions other than <1>: C_IE register's interrupt enable flag = 1), interrupts will occur under the following conditions (m = 00 to 31). <1> Message-related operation has succeeded * When a message has been received in the receive message buffer * When a remote frame has been received in the transmit message buffer (only when auto acknowledge mode has not been set, i.e., when the M_CTRLm register's RMDE0 bit = 0) * When a message has been transmitted from the transmit message buffer <2> When a CAN bus error has been detected * Bit error * Bit stuff error * Form error * CRC error * ACK error <3> When the CAN bus mode has been changed * Error passive status elapsed while FCAN was transmitting * Bus off status was set while FCAN was transmitting * Error passive status elapsed while FCAN was receiving <4> Internal error * Overrun error 18.14.2 Interrupts that occur for global CAN interface Interrupts occur for the global CAN interface under the following conditions. * Access to undefined area * When clearing (0) of the GOM bit is attempted with the EFSD bit of the CGST register = 0, when there is even one CAN module not initialized (ISTAT bit of CnCTRL register = 0) * Access to the CAN module register (register name starting with "Cn" (n = 1, 2)), when the GOM bit of the CGST register = 0 * Access to a temporary buffer when the GOM bit of the CGST register = 1 (area after address of CnSYNC register) User's Manual U14665EJ4V0UD 527 CHAPTER 18 FCAN CONTROLLER 18.15 How to Shut Down FCAN Controller The following procedure should be used to stop CAN bus operations in order to stop the clock supply to the CAN interface (to set low power mode). <1> Set FCAN controller initialization mode * Set initialization mode (INIT bit = 1 in CnCTRL register (set INIT bit = 1, clear INIT bit = 0)) (n = 1, 2) <2> Stop time stamp counter * Set TSM bit = 0 in CGST register (set TSM bit = 0, clear TSM bit = 1) <3> Stop CAN interface * Set GOM bit = 0 in CGST register (set GOM bit = 0, clear GOM bit = 1) * Stop CAN clock Caution If the above procedure is not performed correctly, the CAN interface (in active status) can cause operation faults. 528 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER 18.16 Cautions on Use <1> Bit manipulation is prohibited for all FCAN controller registers. <2> Be sure to properly clear (0) all interrupt request flagsNote in the interrupt routine. If these flags are not cleared (0), subsequent interrupt requests may not be generated. Note also that if an interrupt is generated at the same time as a CPU clear operation, that interrupt request flag will not be cleared (0). important to confirm that interrupt request flags have been properly cleared (0). Note See 18.4.9 CAN interrupt pending register (CCINTP), 18.4.10 CAN global interrupt pending register (CGINTP), and 18.4.11 CANn interrupt pending register (CnINTP). <3> When a change occurs on the CAN bus via a setting of the CSTP bit in the CSTOP register while the clock supply to the CPU or peripheral functions is stopped, the CPU can be woken up. <4> Do not read the same register of the FCAN controller twice or more in a row. If the same register is read twice or more in a row, and even if the value of the register is changed while it is being read the second or subsequent time, the new value is not reflected, and the same value as the one read the first time is always read. (Example) Reading the C1CTRL and C1BA registers (i) Correct usage: New value is reflected when C1CTRL is read the second time. C1CTRL read C1BA read C1CTRL read (ii) Incorrect usage: The second read value of C1CTRL is the same as the first read value of C1CTRL. C1CTRL read C1CTRL read C1BA read <5> When receiving a remote frame with an extended ID and storing it in the receive message buffer, the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus. <6> In the PD703075AY, 703076AY, 703078AY, 703079AY, and 70F3079AY, the time stamp function by SOF detection during message transmission/reception cannot be used. Only the time stamp function by EOF detection during message reception can be used for the V850/SF1. However, only the value captured by the M_TIME register is valid when the TSM bit of the CGST register is set to 1 and the TMR bit of the CnCTRL register is set to 1. It is therefore User's Manual U14665EJ4V0UD 529 CHAPTER 18 FCAN CONTROLLER <7> If the OS (OSEK/COM) is not used, be sure to execute the following processing. [When CAN communication is performed using an interrupt routine] * Clear (0) the following interrupt pending bits at the start of the corresponding interrupt routine. * CnINTm bit of CnINTP register (n = 1, 2, m = 0 to 6) * GINTn bit of CGINTP register (n = 1 to 3) * Clear (0) the following enable bits during the corresponding interrupt routine. * E_INTm bit of CnIE register (n = 1, 2, m = 0 to 6) * G_IEn bit of CGIE register (n = 1, 2) [When CAN communication is performed by polling of bits, not using interrupt routines] * The following interrupt mask flags and interrupt enable bits are used when set (1) (do not clear (0) them). * CANMKn bit of CANICn register (n= 1 to 7) * E_INTm bit of CnIE register (n = 1, 2, m = 0 to 6) * G_IEn bit of CGIE register (n = 1, 2) * IE bit of M_CTRLn register (n = 00 to 31) * Clear (0) the following interrupt pending bits in accordance with procedures (i) to (iii) below. * CnINTm bit of CnINTP register (n = 1, 2, m = 0 to 6) * GINTn bit of CGINTP register (n = 1 to 3) (i) Poll the corresponding interrupt request flag. (ii) If the value of the bit in procedure (i) is 1, clear (0) the corresponding interrupt pending bit. (iii) After executing procedure (ii), clear (0) the interrupt request flag. Example CAN reception (i) Poll until the CANIFm bit of the CANICm register becomes 1 (m = 2, 5). (ii) Clear (0) the CnINT1 bit of the CnINTP register (n = 1, 2). (iii) Clear (0) the CANIFm bit of the CANICm register (m = 2, 5). <8> To emulate the FCAN controller using the emulation board (IE-703079-MC-EM1), perform the following operations on starting the debugger. * Supply power to the VDD0 pin (GC package: 8-pin, GF package: 11-pin) on the target board before starting the debugger. * Set the memory mapping of the debugger as follows. Attribute: Target memory Mapping address: nFF800H to nFFFFFH (n = 3, 7, B) * When accessing the CAN memory, do not mask WAIT and HLDRQ. <9> Port modes (P114 to P117) or alternate functions (CAN transmit/receive pins: CANRX1, CANRX2, CANTX1, CANTX2) can be selected by the port alternate function control register (PAC) for the P114/CANTX1, P115/CANRX1, P116/CANTX2, and P117/CANRX2 pins. In port mode, the CAN transmit/receive signals internally pulled down to low level. To shift the CAN controller to the initialization mode or CAN standby mode, the CAN bus must be the recessive level. Therefore, when the CAN receive pins are in the port mode and the dominant level of the CAN receive pins (CANRX1, CANRX2) is set to low level (DLEVR bit of CnCTRL register = 0), the CAN controller cannot be shift to the initialization mode or CAN standby mode. 530 User's Manual U14665EJ4V0UD CHAPTER 18 FCAN CONTROLLER [Countermeasure] When using the CAN controller, set the CAN transmit/receive pins before the CAN controller initialization after a reset is released, and always retain the status in which the CAN transmit/receive pins are selected. Similarly, when re-initialization of the CAN controller after the CPU standby mode is released, set the CAN transmit/receive pins before the CAN controller initialization. User's Manual U14665EJ4V0UD 531 CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Analog input voltage Output voltage Output current, low VAN VO IOL Per pin Total for all pins Output current, high IOH Per pin Total for P00, P05 to P07, P20 to P27, P30 to P34, P90 to P96 and their alternate-function pins Total for P01 to P04, P10 to P15, P40 to P47, P50 to P57, P60 to P65, P100 to P107, P110 to P117 and their alternate-function pins Operating ambient temperature TA Normal operation mode Flash memory programming mode (PD70F3079AY and 70F3079Y) Tstg Note 3 -40 to +85 -20 to +85 -65 to +150 -40 to +125 C C C C -25 mA VPP pin (PD70F3079AY and 70F3079Y only) Note 2 (ADCVDD pin) Conditions VDD0, PORTVDD, ADCVDD pins Ratings -0.3 to +6.0 -0.3 to VDD +0.3 -0.3 to +8.5 -0.3 to VDD +0.3 Note 1 Note 1 Unit V V V V V mA mA mA mA -0.3 to VDD + 0.3 8.0 25 -8.0 -25 Note 1 Storage temperature PD70F3079AY, 70F3079Y Notes 1. 2. 3. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Ports 7, 8, and their alternate-function pins PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. However, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Capacitance (TA = 25C, VDD0 = PORTVDD = ADCVDD = GND0 = GND1 = GND2 = PORTGND = ADCGND) Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO fC = 1 MHz Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 532 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS 19.1 Normal Operation Mode Operating Conditions (1) Operating voltage Parameter Supply voltage Symbol VDD0 0.5 fCPU 16 MHz, fXT = 32.768 kHz, when all functions are operating (except the A/D converter) 0.5 fCPU 12 MHz, fXT = 32.768 kHz, when all functions are operating (except the A/D converter) PORTVDD 0.5 fCPU 16 MHz, fXT = 32.768 kHz Conditions MIN. 4.0 TYP. MAX. 5.5 Unit V PD703078Y, 703079Y, 70F3079AY PD70F3079Y PD703075AY, 703076AY, 703078AY, 703079AY 4.5 3.5 5.5 5.5 V V PD70F3079Y PD703078Y, 703079Y 4.0 3.5 5.5 5.5 V V PD703078Y, 703079Y, 70F3079AY 4.0 5.5 V PD70F3079Y PD703075AY, 703076AY, 703078AY, 703079AY 0.5 fCPU 12 MHz, fXT = 32.768 kHz ADCVDD 4.5 3.5 5.5 5.5 V V PD70F3079Y PD703078Y, 703079Y 4.0 3.5 4.5 4.0 5.5 5.5 5.5 5.5 V V V V When the A/D converter is operating, VDD0 = ADCVDD When the A/D converter is stopped PD703078Y, 703079Y, 70F3079AY, 70F3079Y PD703075AY, 703076AY, 703078AY, 703079AY 3.5 5.5 V (2) CPU operating frequency Parameter CPU operating frequency Symbol fCPU Conditions Main clock operation Subclock operation MIN. 0.5 32.768 TYP. MAX. 16 Unit MHz kHz User's Manual U14665EJ4V0UD 533 CHAPTER 19 ELECTRICAL SPECIFICATIONS Recommended Oscillator (1) Main clock oscillator (TA = -40 to +85C) (a) Connection of ceramic resonator or crystal resonator X1 X2 Parameter Oscillation frequency Oscillation stabilization time Symbol fXX - - Conditions MIN. 4 TYP. MAX. 16 Unit MHz s s Upon reset release Upon STOP mode release Note 1 Note 2 Notes 1. 2 /fXX: PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY 18 221/fXX: PD703078Y, 703079Y, 70F3079Y Since the value after reset differs, refer to 10.3 (1) Oscillation stabilization time selection register (OSTS) for details. 2. The TYP. value differs depending on the setting of the oscillation stabilization time selection register (OSTS). Cautions 1. The main clock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 534 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (2) Subclock oscillator (TA = -40 to +85C) (a) Connection of crystal resonator XT1 XT2 Parameter Oscillation frequency Oscillation stabilization time Symbol fXT - Conditions MIN. TYP. 32.768 MAX. Unit kHz s When reset is released 10 Cautions 1. The subclock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Sufficiently evaluate the matching between the resonator and the V850/SF1. User's Manual U14665EJ4V0UD 535 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = ADCGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, ADCVDD = 4.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, ADCVDD = 4.5 to 5.5 V) (1/2) Parameter Input voltage, high Symbol VIH1 VIH2 Input voltage, low VIL1 VIL2 Output voltage, high VOH Note 1 Note 2 Note 1 Note 2 Note 3 IOH1 = -100 A IOH1 = -1 mA Output voltage, low VOL Note 3 IOL1 = 1 mA IOL1 = 3 mA Input leakage current, high Input leakage current, low Output off-leakage current Pull-up resistor IIH1 IIL1 IL1 RL1 Note 4 Note 4 Note 5 Note 6 VIN = VDD VIN = 0 V VOH = VDD VIN = 0 V 10 30 Conditions MIN. 0.7VDD 0.8VDD 0 0 VDD - 0.5 VDD - 1.0 0.5 1.0 5.0 -5.0 5.0 100 TYP. MAX. VDD VDD 0.3VDD 0.2VDD Unit V V V V V V V V A A A k Notes 1. 2. 3. 4. 5. 6. P11, P14, P21, P24, P27, P34, P40 to P47, P50 to P57, P60 to P65, P70 to P77, P80 to P83, P90 to P96, P100, P104, P107, P110 to P114, P116, and their alternate-function pins P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25, P26, P30 to P33, P101 to P103, P105, P106, P115, P117, RESET, and their alternate-function pins All output pins and their alternate-function pins All input pins and their alternate-function pins P10, P12 (in N-ch open-drain mode) P100 to P107 (in key return mode) 536 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = ADCGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, ADCVDD = 4.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, ADCVDD = 4.5 to 5.5 V) (2/2) Parameter Supply current Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 Conditions In normal operation mode In HALT mode In IDLE mode Note 2 Note 1 MIN. TYP. 15 9 0.5 15 MAX. 30 20 3 100 200 180 160 50 20 4 100 600 300 200 Unit mA mA mA PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y Note 3 In STOP mode Note 4 A A A A mA mA mA In normal mode (subclock operation) In HALT mode (subclock operation) In IDLE mode (subclock operation) In normal operation mode In HALT mode In IDLE mode Note 2 Note 1 Note 5 50 30 20 25 9 0.5 15 Note 6 Note 7 PD70F3079AY, 70F3079Y IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 Note 3 In STOP mode Note 4 A A A A In normal mode (subclock operation) In HALT mode (subclock operation) In IDLE mode (subclock operation) Note 5 200 150 90 Note 6 Note 7 Notes 1. 2. 3. 4. 5. 6. 7. fCPU = fXX = 16 MHz, VIN = VCPUREG, peripheral functions operating (except FCAN) fCPU = fXX = 16 MHz, VIN = VCPUREG, CPU stopped, peripheral functions operating (except FCAN) fXX = 16 MHz, VIN = VCPUREG, all peripheral functions stopped (watch timer operating) fXT = 32.768 kHz, VIN = VCPUREG, main clock oscillator stopped, all peripheral functions stopped (watch timer operating with subclock) fCPU = fXT = 32.768 kHz, VIN = VCPUREG, main clock oscillator stopped, all peripheral functions operating (except FCAN) fCPU = fXT = 32.768 kHz, VIN = VCPUREG, main clock oscillator stopped, CPU stopped, peripheral functions operating (except FCAN) fXT = 32.768 kHz, VIN = VCPUREG, main clock oscillator stopped, all peripheral functions stopped (watch timer operating) User's Manual U14665EJ4V0UD 537 CHAPTER 19 ELECTRICAL SPECIFICATIONS Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage tDREL VIHDR VILDR All input ports All input ports 0 0.9VDDDR 0 VDDDR 0.1VDDDR ns V V Symbol VDDDR IDDDR tRVD tFVD tHVD STOP mode STOP mode Conditions Note MIN. 2.2 TYP. MAX. 5.5 Unit V (no functions operating) (no functions operating) Note 10 200 200 0 100 A s s ms Note Subclock stopped Setting STOP mode VDD tFVD tHVD V DDDR tRVD tDREL RESET (input) V IHDR STOP mode release interrupt (NMI, etc.) (Released by falling edge) V IHDR STOP mode release interrupt (NMI, etc.) (Released by rising edge) V ILDR 538 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = ADCGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, ADCVDD = 4.0 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = ADCVDD = 4.0 to 5.5 V) AC Test Input Test Points (VDD: VDD0, PORTVDD) VDD Input signal 0V VIH Test points VIL VIH VIL AC Test Output Test Points (VDD: VDD0, PORTVDD) VDD Output signal 0V VOH Test points VOL VOH VOL Load Conditions DUT (Device under test) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. User's Manual U14665EJ4V0UD 539 CHAPTER 19 ELECTRICAL SPECIFICATIONS (1) Clock timing (a) TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol <1> <2> <3> <4> <5> tCYK tWKH tWKL tKR tKF Conditions MIN. 62.5 ns 0.4tCYK - 12 0.4tCYK - 12 12 12 MAX. 31 s ns ns ns ns Unit (b) TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol <1> <2> <3> <4> <5> tCYK tWKH tWKL tKR tKF Conditions MIN. 83 ns 0.4tCYK - 15 0.4tCYK - 15 15 15 MAX. 31 s ns ns ns ns Unit (c) (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703079AY: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol <1> <2> <3> <4> <5> tCYK tWKH tWKL tKR tKF Conditions MIN. 62.5 ns 0.4tCYK - 15 0.4tCYK - 15 15 15 MAX. 31 s ns ns ns ns Unit <1> <2> CLKOUT (output) <4> <5> <3> 540 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (2) Output waveform (other than port 4, port 5, port 6, port 9, and CLKOUT) (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter Output rise time Output fall time Symbol <6> <7> tOR tOF Conditions MIN. MAX. 35 35 Unit ns ns <6> <7> Output signal (3) Reset timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter RESET pin high-level width RESET pin low-level width Symbol <8> <9> tWRSH tWRSL Conditions MIN. 500 500 MAX. Unit ns ns <8> <9> RESET (input) User's Manual U14665EJ4V0UD 541 CHAPTER 19 ELECTRICAL SPECIFICATIONS (4) Bus timing (a) Clock asynchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from DSTB to address float Data input setup time from address Data input setup time from DSTB Data input setup time from ASTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> WAIT hold time (from address) <28> <29> WAIT setup time (to ASTB) <30> <31> WAIT hold time (from ASTB) <32> <33> HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <34> <35> <36> <37> <38> tSAST tHSTA tFDA tSAID tSDID tSASID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 n 1 tSSTWT2 tHSTWT1 n 1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 nT (1 + n)T T + 10 T - 15 0 1.5T 0.5T (2n + 7.5)T + 25 1.5T + 25 n1 (0.5 + n)T (1.5 + n)T T - 40 (1 + n)T - 40 n1 (1 + n)T - 30 T - 15 1.5T - 55 (1.5 + n)T - 55 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 20 T - 15 20 Conditions MIN. 0.5T - 25 0.5T - 15 0 (2 + n)T - 55 (1 + n)T - 45 (1.5 + n)T - 62 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T: 1/fCPU (fCPU: CPU clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle cycles inserted in the bus cycle. 4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 5. For the number of wait clocks to be inserted, refer to 6.5.3 Relationship between programmable wait and external wait. 542 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Clock asynchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from DSTB to address float Data input setup time from address Data input setup time from DSTB Data input setup time from ASTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> WAIT hold time (from address) <28> <29> WAIT setup time (to ASTB) <30> <31> WAIT hold time (from ASTB) <32> <33> HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <34> <35> <36> <37> <38> tSAST tHSTA tFDA tSAID tSDID tSASID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 n 1 tSSTWT2 tHSTWT1 n 1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 nT (1 + n)T T + 10 T - 25 0 1.5T 0.5T (2n + 7.5)T + 25 1.5T + 25 n1 (0.5 + n)T (1.5 + n)T T - 55 (1 + n)T - 55 n1 (1 + n)T - 35 T - 25 1.5T - 70 (1.5 + n)T - 70 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 35 T - 15 25 Conditions MIN. 0.5T - 32 0.5T - 22 0 (2 + n)T - 70 (1 + n)T - 60 (1.5 + n)T - 70 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T: 1/fCPU (fCPU: CPU clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle cycles inserted in the bus cycle. 4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 5. For the number of wait clocks to be inserted, refer to 6.5.3 Relationship between programmable wait and external wait. User's Manual U14665EJ4V0UD 543 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Clock asynchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703079AY: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from DSTB to address float Data input setup time from address Data input setup time from DSTB Data input setup time from ASTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> WAIT hold time (from address) <28> <29> WAIT setup time (to ASTB) <30> <31> WAIT hold time (from ASTB) <32> <33> HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <34> <35> <36> <37> <38> tSAST tHSTA tFDA tSAID tSDID tSASID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 n1 nT (1 + n)T T + 10 T - 15 0 1.5T 0.5T (2n + 7.5)T + 25 1.5T + 25 n1 n1 (0.5 + n)T (1.5 + n)T T - 40 (1 + n)T - 40 n1 (1 + n)T - 30 T - 20 1.5T - 55 (1.5 + n)T - 55 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 20 (1 + n)T - 20 T - 20 25 Conditions MIN. 0.5T - 27 0.5T - 15 0 (2 + n)T - 55 (1 + n)T - 45 (1.5 + n)T - 67 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T: 1/fCPU (fCPU: CPU clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle cycles inserted in the bus cycle. 4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 5. For the number of wait clocks to be inserted, refer to 6.5.3 Relationship between programmable wait and external wait. 544 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Clock synchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to data output WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK <51> tDKHA 35 ns Symbol <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> tDKA tFKA tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF 25 5 20 5 19 Conditions MIN. 0 -12 0 0 20 5 35 MAX. 35 15 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (e) Clock synchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703078Y, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to data output WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK <51> tDKHA 40 ns Symbol <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> tDKA tFKA tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF 29 5 24 5 19 Conditions MIN. 0 -17 0 0 20 5 45 MAX. 45 15 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U14665EJ4V0UD 545 CHAPTER 19 ELECTRICAL SPECIFICATIONS (f) Clock synchronous (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703079AY: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to data output WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK <51> tDKHA 35 ns Symbol <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> tDKA tFKA tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF 25 5 20 5 19 Conditions MIN. 0 -12 0 0 22 5 35 MAX. 35 15 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 546 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (g) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) T1 CLKOUT (output) T2 TW T3 <39> A16 to A21 (output) Note (output) <13> <40> <43> <44> AD0 to AD15 (I/O) Address Data <41> <10> <11> <15> ASTB (output) <17> <41> <22> <42> <12> <16> <14> <42> <19> <18> <20> DSTB (output) <21> <46> <30><46> <47> <32> <31> <33> WAIT (input) <26> <28> <27> <29> <47> Note R/W, UBEN, LBEN Remark Broken lines indicate high impedance. User's Manual U14665EJ4V0UD 547 CHAPTER 19 ELECTRICAL SPECIFICATIONS (h) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) T1 CLKOUT (output) T2 TW T3 <39> A16 to A21 (output) Note (output) <45> AD0 to AD15 (I/O) Address Data <41> <10> <11> <41> ASTB (output) <22> <42> <23> <16> <24> <42> <19> <25> DSTB (output) <21> <46> <30><46> <47> <32> <31> <33> WAIT (input) <26> <28> <27> <29> <47> Note R/W, UBEN, LBEN Remark Broken lines indicate high impedance. 548 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (i) Bus hold timing TH CLKOUT (output) TH TH TH TI <48> <48> <49> HLDRQ (input) <51> <37> HLDAK (output) <35> <50> A16 to A19 (output) Note (output) <34> <51> <38> <36> AD0 to AD15 (I/O) Data ASTB (output) DSTB (output) Note R/W, UBEN, LBEN Remark Broken lines indicate high impedance. User's Manual U14665EJ4V0UD 549 CHAPTER 19 ELECTRICAL SPECIFICATIONS (5) Interrupt timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter NMI high-level width NMI low-level width INTPn high-level width Symbol <52> <53> <54> tWNIH tWNIL tWITH n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination INTPn low-level width <55> tWITL n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination 3Tsmp + 20 ns 3T + 20 ns 500 ns 3Tsmp + 20 ns 3T + 20 ns Conditions MIN. 500 500 500 MAX. Unit ns ns ns Remarks 1. T: 1/fXX 2. Tsmp: Noise elimination sampling clock cycle <52> <53> NMI (input) <54> <55> INTPn (input) Remark n = 0 to 6 550 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (6) RPU timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter TIn0, TIn1 high-level width TIn0, TIn1 low-level width TIm high-level width TIm low-level width Symbol <56> <57> <58> <59> tTIHn tTILn tTIHm tTILm Conditions n = 0, 1, 7 n = 0, 1, 7 m = 2 to 5 m = 2 to 5 MIN. 2Tsam + 20 2Tsam + 20 3T + 20 3T + 20 Note MAX. Unit ns ns ns ns Note Note Tsam (count clock cycle) can select the following cycles by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0, n1 (PRMn0, PRMn1). When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T cycle However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T. Remark T: 1/fXX <56> <57> TIn0, TIn1 (input) <58> <59> TIm (input) Remark n = 0, 1, 7 m = 2 to 5 User's Manual U14665EJ4V0UD 551 CHAPTER 19 ELECTRICAL SPECIFICATIONS (7) Asynchronous serial interface (UART0, UART1) timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol <60> <61> <62> tKCY13 tKH13 tKL13 Conditions MIN. 200 80 80 MAX. Unit ns ns ns Remark n = 0, 1 <60> <61> <62> ASCKn (input) Remark n = 0, 1 552 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (8) 3-wire serial interface (CSI0, CSI1, CSI3) timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) (a) Master mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <63> <64> <65> <66> <67> <68> tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Note Conditions MIN. 400 140 140 50 50 80 100 MAX. Unit ns ns ns ns ns ns ns Note PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V n = 0, 1, 3 Remark (b) Slave mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <63> <64> <65> <66> <67> <68> tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 Note Conditions MIN. 400 140 140 50 50 80 100 MAX. Unit ns ns ns ns ns ns ns Note PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V n = 0, 1, 3 Remark User's Manual U14665EJ4V0UD 553 CHAPTER 19 ELECTRICAL SPECIFICATIONS <63> <64> <65> SCKn (I/O) <66> <67> SIn (input) Input data <68> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1, 3 554 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (9) 3-wire variable length serial interface (CSI4) timing (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) (a) Master mode Parameter SCK4 cycle SCK4 high-level width SCK4 low-level width SI4 setup time (to SCK4) SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output Symbol <69> <70> <71> <72> <73> <74> tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Note Conditions MIN. 200 60 60 25 20 55 70 MAX. Unit ns ns ns ns ns ns ns Note PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V (b) Slave mode Parameter SCK4 cycle SCK4 high-level width SCK4 low-level width SI4 setup time (to SCK4) SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output Symbol <69> <70> <71> <72> <73> <74> tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 Note Conditions MIN. 200 60 60 25 20 55 70 MAX. Unit ns ns ns ns ns ns ns Note PD703078Y, 703079Y: VDD0 = PORTVDD = 4.0 to 5.5 V, PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V <69> <70> <71> SCK4 (I/O) <72> <73> SI4 (input) Input data <74> SO4 (output) Output data Remark Broken lines indicate high impedance. User's Manual U14665EJ4V0UD 555 CHAPTER 19 ELECTRICAL SPECIFICATIONS (10) I2C bus mode (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) (1/2) Parameter Symbol Normal Mode MIN. SCL0 clock frequency Bus-free time (between stop/start conditions) Hold time Note 1 High-Speed Mode MIN. 0 1.3 MAX. 400 - - - - - - Note 3 Unit MAX. 100 - - - - - - - - 1000 300 - - - <75> fCLK tBUF 0 4.7 kHz s s s s s s s ns ns ns <76> <77> <78> <79> tHD:STA tLOW tHIGH tSU:STA 4.0 4.7 4.0 4.7 0.6 1.3 0.6 0.6 - Note 2 SCL0 clock low-level width SCL0 clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line 2 <80> tHD:DAT 5.0 0 <81> <82> <83> <84> <85> - tSU:DAT tR tF tSU:STO tSP Note 2 0 0.9 250 - - 4.0 - - 100 Note 4 - Note 5 20 + 0.1Cb 300 300 - 50 20 + 0.1Cb 0.6 0 - Note 5 s ns Cb 400 400 pF Notes 1. 2. 3. 4. At the start condition, the first clock pulse is generated after the hold time. The system requires a minimum of 300 ns hold time internally for the SDA0 signal (at VIHmin.. of SCL0 signal) in order to occupy the undefined area at the falling edge of SCL0. If the system does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the high-speed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCL0 signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCL0 signal's low state hold time: Transmit the following data bit to the SDA0 line prior to the SCL0 line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) 556 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (10) I2C bus mode (TA = -40 to +85C, GND0 = GND1 = GND2 = PORTGND = 0 V, PD703075AY, 703076AY, 703078AY, 703078Y, 703079AY, 703079Y: VDD0 = PORTVDD = 3.5 to 5.5 V, PD70F3079AY, 70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) (2/2) <77> <78> SCL0 (I/O) <83> <76> <82> <80> <81> <79> <76> <85> <84> SDA0 (I/O) <75> Stop condition Start condition <83> <82> Restart condition Stop condition User's Manual U14665EJ4V0UD 557 CHAPTER 19 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics (TA = -40 to +85C, VDD0 = ADCVDD = 4.5 to 5.5 V, GND0 = GND1 = GND2 = ADCGND = 0 V, Output pin load capacitance: CL = 50 pF) Parameter Resolution Overall error Note 1 Symbol - - tCONV AINL AINL ADM2 = 01H ADM2 = 01H ADM2 = 01H ADCVDD pin ADM2 = 01H Conditions MIN. 10 TYP. 10 MAX. 10 1.0 Unit bit %FSR Conversion time Zero-scale error Full-scale error Note 1 5 10 0.4 0.6 6.0 6.0 s %FSR %FSR LSB LSB V V mA Note 1 Integral linearity error Note 2 INL DNL AVDD VIAN AIDD Differential linearity error Note 2 Analog power supply voltage Analog input voltage ADCVDD current 4.5 0 5.5 ADCVDD 4 8 ADM2 = 01H Notes 1. 2. Excluding quantization error (0.05 %FSR) Excluding quantization error (0.5 LSB) Remarks 1. LSB: Least Significant Bit FSR: Full Scale Range 2. ADM2: A/D converter mode register 2 Power-On-Clear Circuit, 4.5 V Detection Flag Characteristics (TA = -40 to +85C) Parameter POC circuit detection voltage Symbol VPOCH VPOCL VM45 flag setting voltage VM45 Conditions CPU operation STOP mode MIN. 2.7 1.5 3.7 TYP. 3.0 1.8 4.2 MAX. 3.3 2.1 4.5 Unit V V V 558 User's Manual U14665EJ4V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS 19.2 Flash Memory Programming Mode (PD70F3079AY and 70F3079Y Only) Basic Characteristics (TA = -20 to +85C, VDD0 = ADCVDD = PORTVDD = 4.5 to 5.5 V, GND0 = GND1 = GND2 = ADCGND = PORTGND = 0 V) Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Overall erase time per area Symbol VPP2 IDD IPP tER tERA Conditions During flash memory programming VPP = VPP2 VPP = VPP2 Note 1 When the step erase time = 0.2 s, Note 2 Write-back time Number of write-backs per writeback command tWB CWB Note 3 When the write-back time = 1 ms, Note 4 1 300 ms Count/ write-back command Number of erase/write-backs Step writing time Overall writing time per word CERWB tWR tWRW Note 5 When the step writing time = 20 s (1 word = 4 bytes), Note 6 Number of rewrites per area CERWR 1 erase + 1 write after erase = 1 rewrite, Note 7 100 Count/ area 20 20 200 16 Count 0.2 20 fXX = 16 MHz MIN. 7.5 TYP. 7.8 MAX. 8.1 53 100 Unit V mA mA s s/area s s/word Notes 1. 2. 3. 4. 5. 6. 7. The recommended setting value of the step erase time is 0.2 s. The prewrite time prior to erasure and the erase verify time (write-back time) are not included. The recommended setting value of the write-back time is 1 ms. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count must be the maximum value minus the number of commands issued. The recommended setting value of the step writing time is 20 s. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remarks 1. The operating clock range during programming flash memory is the same as normal operation. 2. When the PG-FP3 or PG-FP4 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 3. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH User's Manual U14665EJ4V0UD 559 CHAPTER 20 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S CD Q R 100 1 26 25 F G P H I M J K S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 +7 3 -3 1.60 MAX. S100GC-50-8EU, 8EA-2 560 User's Manual U14665EJ4V0UD CHAPTER 20 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S CD Q R 100 1 31 30 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. P100GF-65-3BA1-4 User's Manual U14665EJ4V0UD 561 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS The V850/SF1 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 21-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD703075AYGC-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) PD703076AYGC-xxx-8EU: PD703078AYGC-xxx-8EU: PD703078YGC-xxx-8EU: PD703079AYGC-xxx-8EU: PD703079YGC-xxx-8EU: PD70F3079AYGC-8EU: PD70F3079YGC-8EU: Soldering Method 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 days Note IR35-107-2 (after that, prebake at 125C for 10 to 72 hours) VP15-107-2 VPS Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125C for 10 to 72 hours) - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Remark Do not use different soldering methods together (except for partial heating). The recommended soldering conditions of (A) grade products are the same as those of standard products. 562 User's Manual U14665EJ4V0UD CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS Table 21-1. Surface Mounting Type Soldering Conditions (2/2) (2) PD70F3079AYGF-3BA: 100-pin plastic QFP (14 x 20) PD70F3079YGF-3BA: Soldering Method 100-pin plastic QFP (14 x 20) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 days Note IR35-207-2 (after that, prebake at 125C for 20 to 72 hours) VP15-207-2 VPS Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125C for 20 to 72 hours) - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (3) PD703075AYGF-xxx-3BA: 100-pin plastic QFP (14 x 20) PD703076AYGF-xxx-3BA: PD703078AYGF-xxx-3BA: PD703078YGF-xxx-3BA: PD703079AYGF-xxx-3BA: PD703079YGF-xxx-3BA: Soldering Method 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 days Note IR35-207-2 (after that, prebake at 125C for 20 to 72 hours) VP15-207-2 VPS Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125C for 20 to 72 hours) WS60-207-1 Wave soldering Soldering bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 days Note (after that, prebake at 125C for 20 to 72 hours) - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U14665EJ4V0UD 563 APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the shape of parts mounted on the target system as shown below. Figure A-1. 100-Pin Plastic LQFP (Fine Pitch) (14 x 14) Side view In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703079-MC-EM1 230 mm Note Conversion connector YQGUIDE YQPACK100SD NQPACK100SD Target system Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm). Top view IE-703002-MC Target system Pin 1 position IE-703079-MC-EM1 YQPACK100SD, NQPACK100SD, YQGUIDE Connection condition diagram IE-703079-MC-EM1 Connect to IE-703002-MC. Pin 1 position 130 mm YQGUIDE YQPACK100SD NQPACK100SD 13.3 mm 48 mm 35 mm 55 mm 41 mm Target system 564 User's Manual U14665EJ4V0UD APPENDIX A NOTES ON TARGET SYSTEM DESIGN Figure A-2. 100-Pin Plastic QFP (14 x 20) Side view In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703079-MC-EM1 230 mm Note Conversion connector SWEX-100SD/GF-N17D 264 5 mm 44 mm 56 mm YQGUIDE YQPACK100RB NQPACK100RB Target system Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm). Top view SWEX-100SD/GF-N17D Target system 38 mm Pin 1 position 44 mm YQPACK100RB, NQPACK100RB, YQGUIDE Connection condition diagram SWEX-100SD/GF-N17D 24.5 mm YQPACK100RB NQPACK100RB 19.7 mm 44 mm 38 mm Target system User's Manual U14665EJ4V0UD 565 APPENDIX B REGISTER INDEX (1/8) Symbol ADCR ADCRH ADIC ADM1 ADM2 ADS ASIM0 ASIM1 ASIS0 ASIS1 BCC BRGC0 BRGC1 BRGCK4 BRGCN4 BRGMC00 BRGMC01 BRGMC10 BRGMC11 C1BA C1BRP C1CTRL C1DEF C1DINF C1ERC C1IE C1INTP C1LAST C1MASKH0 C1MASKH1 C1MASKH2 C1MASKH3 C1MASKL0 C1MASKL1 C1MASKL2 C1MASKL3 A/D conversion result register A/D conversion result register H (higher 8 bits) Interrupt control register A/D converter mode register 1 A/D converter mode register 2 Analog input channel specification register Asynchronous serial interface mode register 0 Asynchronous serial interface mode register 1 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Bus cycle control register Baud rate generator control register 0 Baud rate generator control register 1 Baud rate generator output clock selection register 4 Baud rate generator source clock selection register 4 Baud rate generator mode control register 00 Baud rate generator mode control register 01 Baud rate generator mode control register 10 Baud rate generator mode control register 11 CAN1 bus active register CAN1 bit rate prescaler register CAN1 control register CAN1 definition register CAN1 bus diagnostic information register CAN1 error count register CAN1 interrupt enable register CAN1 interrupt pending register CAN1 information register CAN1 address mask 0 register H CAN1 address mask 1 register H CAN1 address mask 2 register H CAN1 address mask 3 register H CAN1 address mask 0 register L CAN1 address mask 1 register L CAN1 address mask 2 register L CAN1 address mask 3 register L Name Unit ADC ADC ADC ADC ADC ADC UART UART UART UART BCU BRG BRG BRG BRG BRG BRG BRG BRG FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN Page 348 348 162 350 350 353 317 317 318 318 136 319 319 340 339 320 320 320 320 467 468 455 460 471 464 465 441 463 453 453 453 453 453 453 453 453 566 User's Manual U14665EJ4V0UD APPENDIX B REGISTER INDEX (2/8) Symbol C1SYNC C2BA C2BRP C2CTRL C2DEF C2DINF C2ERC C2IE C2INTP C2LAST C2MASKH0 C2MASKH1 C2MASKH2 C2MASKH3 C2MASKL0 C2MASKL1 C2MASKL2 C2MASKL3 C2SYNC CANIC1 CANIC2 CANIC3 CANIC4 CANIC5 CANIC6 CANIC7 CCINTP CGCS CGIE CGINTP CGMSR CGMSS CGST CGTSC CORAD0 CORAD1 CORAD2 CORAD3 CAN1 synchronization control register CAN2 bus active register CAN2 bit rate prescaler register CAN2 control register CAN2 definition register CAN2 bus diagnostic information register CAN2 error count register CAN2 interrupt enable register CAN2 interrupt pending register CAN2 information register CAN2 address mask 0 register H CAN2 address mask 1 register H CAN2 address mask 2 register H CAN2 address mask 3 register H CAN2 address mask 0 register L CAN2 address mask 1 register L CAN2 address mask 2 register L CAN2 address mask 3 register L CAN2 synchronization control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register CAN interrupt pending register CAN main clock select register CAN global interrupt enable register CAN global interrupt pending register CAN message search result register CAN message search start register CAN global status register CAN time stamp count register Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Name Unit FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN INTC INTC INTC INTC INTC INTC INTC FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN CPU CPU CPU CPU Page 472 467 468 455 460 471 464 465 441 463 453 453 453 453 453 453 453 453 472 162 162 162 162 162 162 162 439 448 447 440 451 451 444 450 390 390 390 390 User's Manual U14665EJ4V0UD 567 APPENDIX B REGISTER INDEX (3/8) Symbol CORCN CORRQ CR00 CR01 CR10 CR11 CR2 CR3 CR4 CR5 CR6 CR70 CR71 CRC0 CRC1 CRC7 CSIB4 CSIC0 CSIC1 CSIC3 CSIC4 CSIM0 CSIM1 CSIM3 CSIM4 CSIS0 CSIS1 CSIS3 CSTOP DBC0 DBC1 DBC2 DBC3 DBC4 DBC5 DCHC0 DCHC1 Correction control register Correction request register Capture/compare register 00 Capture/compare register 01 Capture/compare register 10 Capture/compare register 11 16-bit compare register 2 16-bit compare register 3 16-bit compare register 4 16-bit compare register 5 16-bit compare register 6 Capture/compare register 70 Capture/compare register 71 Capture/compare control register 0 Capture/compare control register 1 Capture/compare control register 7 Variable-length serial setting register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Serial operation mode register 0 Serial operation mode register 1 Serial operation mode register 3 Variable-length serial control register Serial clock selection register 0 Serial clock selection register 1 Serial clock selection register 3 CAN stop register DMA byte count register 0 DMA byte count register 1 DMA byte count register 2 DMA byte count register 3 DMA byte count register 4 DMA byte count register 5 DMA channel control register 0 DMA channel control register 1 Name Unit CPU CPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU CSI INTC INTC INTC INTC CSI CSI CSI CSI CSI CSI CSI FCAN DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Page 389 389 186 187 186 187 222 222 222 222 222 186 187 190 190 190 338 162 162 162 162 251 251 251 337 252 252 252 443 375 375 375 375 375 375 376 376 568 User's Manual U14665EJ4V0UD APPENDIX B REGISTER INDEX (4/8) Symbol DCHC2 DCHC3 DCHC4 DCHC5 DIOA0 DIOA1 DIOA2 DIOA3 DIOA4 DIOA5 DMAIC0 DMAIC1 DMAIC2 DMAIC3 DMAIC4 DMAIC5 DMAS DRA0 DRA1 DRA2 DRA3 DRA4 DRA5 DWC ECR EGN0 EGP0 IIC0 IICC0 IICCE0 IICCL0 IICS0 IICX0 ISPR KRIC KRM MM DMA channel control register 2 DMA channel control register 3 DMA channel control register 4 DMA channel control register 5 DMA peripheral I/O address register 0 DMA peripheral I/O address register 1 DMA peripheral I/O address register 2 DMA peripheral I/O address register 3 DMA peripheral I/O address register 4 DMA peripheral I/O address register 5 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register DMA trigger expansion register DMA internal RAM address register 0 DMA internal RAM address register 1 DMA internal RAM address register 2 DMA internal RAM address register 3 DMA internal RAM address register 4 DMA internal RAM address register 5 Data wait control register Interrupt source register Falling edge specification register 0 Rising edge specification register 0 IIC shift register 0 IIC control register 0 IIC clock expansion register 0 IIC clock selection register 0 IIC status register 0 IIC function expansion register 0 In-service priority register Interrupt control register Key return mode register Memory expansion mode register Name Unit DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC INTC INTC INTC INTC INTC INTC DMAC DMAC DMAC DMAC DMAC DMAC DMAC BCU CPU INTC INTC IC IC IC IC IC IC INTC INTC KR Port 2 2 2 2 2 2 Page 376 376 376 376 372 372 372 372 372 372 162 162 162 162 162 162 375 372 372 372 372 372 372 134 50 97, 155 96, 155 258, 270 260 268 268 265 268 165 162 181 64 User's Manual U14665EJ4V0UD 569 APPENDIX B REGISTER INDEX (5/8) Symbol M_CONF00 to M_CONF31 M_CTRL00 to M_CTRL31 M_DATA000 CAN message data registers 000 to 317 to M_DATA317 M_DLC00 to M_DLC31 M_IDH00 to M_IDH31 M_IDL00 to M_IDL31 M_STAT00 to M_STAT31 M_TIME00 to M_TIME31 NCC OSTS P0 P1 P10 P11 P2 P3 P4 P5 P6 P7 P8 P9 PAC PCC PF1 PIC0 PIC1 Noise elimination control register Oscillation stabilization time selection register Port 0 Port 1 Port 10 Port 11 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port alternate-function control register Processor clock control register Port 1 function register Interrupt control register Interrupt control register User's Manual U14665EJ4V0UD Name CAN message configuration registers 00 to 31 Unit FCAN Page 433 CAN message control registers 00 to 31 FCAN 425 FCAN 429 CAN message data length registers 00 to 31 FCAN 423 CAN message ID registers H00 to H31 FCAN 431 CAN message ID registers L00 to L31 FCAN 431 CAN message status registers 00 to 31 FCAN 435 CAN message time stamp registers 00 to 31 FCAN 427 INTC WDT Port Port Port Port Port Port Port Port Port Port Port Port Port CG Port INTC INTC 168 81, 243 94 98 118 121 102 105 108 108 111 113 113 115 122 78 99 162 162 570 APPENDIX B REGISTER INDEX (6/8) Symbol PIC2 PIC3 PIC4 PIC5 PIC6 PM0 PM1 PM10 PM11 PM2 PM3 PM4 PM5 PM6 PM9 POCS PRCMD PRM00 PRM01 PRM10 PRM11 PRM70 PRM71 PSC PSW PU10 RX0 RX1 RXB0 RXB1 SAR SC_STAT00 to SC_STAT31 SERIC0 SERIC1 SIO0 SIO1 SIO3 Interrupt control register Interrupt control register Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 3 User's Manual U14665EJ4V0UD Name Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Port 0 mode register Port 1 mode register Port 10 mode register Port 11 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 9 mode register POC status register Command register Prescaler mode register 00 Prescaler mode register 01 Prescaler mode register 10 Prescaler mode register 11 Prescaler mode register 70 Prescaler mode register 71 Power save control register Program status word Pull-up resistor option register 10 Receive shift register 0 Receive shift register 1 Receive buffer register 0 Receive buffer register 1 Successive approximation register CAN status set/clear registers 00 to 31 Unit INTC INTC INYC INTC INTC Port Port Port Port Port Port Port Port Port Port Reset CG RPU RPU RPU RPU RPU RPU CG CPU Port UART UART UART UART ADC FCAN Page 162 162 162 162 162 96 99 119 122 103 106 109 109 112 115 385 75 193 193 195 195 195 195 80 51 119 315 315 315 315 348 437 INTC INTC CSI CSI CSI 162 162 250 250 250 571 APPENDIX B REGISTER INDEX (7/8) Symbol SIO4 STIC0 STIC1 SVA0 SYS TCL20 TCL21 TCL30 TCL31 TCL40 TCL41 TCL50 TCL51 TCL60 TCL61 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TMC0 TMC1 TMC20 TMC30 TMC40 TMC50 TMC60 TMC7 TMIC00 TMIC01 TMIC10 TMIC11 TMIC2 TMIC3 TMIC4 Variable-length serial I/O shift register 4 Interrupt control register Interrupt control register Slave address register 0 System status register Timer clock selection register 20 Timer clock selection register 21 Timer clock selection register 30 Timer clock selection register 31 Timer clock selection register 40 Timer clock selection register 41 Timer clock selection register 50 Timer clock selection register 51 Timer clock selection register 60 Timer clock selection register 61 16-bit timer register 0 16-bit timer register 1 16-bit counter 2 16-bit counter 3 16-bit counter 4 16-bit counter 5 16-bit counter 6 16-bit timer register 7 16-bit timer mode control register 0 16-bit timer mode control register 1 16-bit timer mode control register 20 16-bit timer mode control register 30 16-bit timer mode control register 40 16-bit timer mode control register 50 16-bit timer mode control register 60 16-bit timer mode control register 7 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Name Unit CSI INTC INTC IC CG RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU RPU INTC INTC INTC INTC INTC INTC INTC 2 Page 335 162 162 258, 270 75 223 223 223 223 223 223 223 223 223 223 185 185 222 222 222 222 222 185 188 188 226 226 226 226 226 188 162 162 162 162 162 162 162 572 User's Manual U14665EJ4V0UD APPENDIX B REGISTER INDEX (8/8) Symbol TMIC5 TMIC6 TMIC70 TMIC71 TOC0 TOC1 TOC7 TXS0 TXS1 VM45C WDCS WDTIC WDTM WTNCS WTNIC WTNIIC WTNM Interrupt control register Interrupt control register Interrupt control register Interrupt control register 16-bit timer output control register 0 16-bit timer output control register 1 16-bit timer output control register 7 Transmit shift register 0 Transmit shift register 1 VM45 control register Watchdog timer clock selection register Interrupt control register Watchdog timer mode register Watch timer clock selection register Interrupt control register Interrupt control register Watch timer mode control register Name Unit INTC INTC INTC INTC RPU RPU RPU UART UART Reset WDT INTC WDT WT INTC INTC WT Page 162 162 162 162 191 191 191 315 315 386 244 162 167, 245 238 162 162 237 User's Manual U14665EJ4V0UD 573 APPENDIX C INSTRUCTION SET LIST * How to read instruction set list This column shows the instruction group. Instructions are divided into instruction groups and described. This column shows instruction mnemonics. This column shows instruction operands (refer to Table C-1). This column shows instruction codes (opcode) in binary format. 32-bit instructions are displayed in 2 lines (refer to Table C-2). This column shows instruction operations (refer to Table C-3). This column shows flag statuses (refer to Table C-4). Flag Instruction Group Mnemonic Operand Opcode Operation CY OV S Z SAT Table C-1. Symbols in Operand Description Symbol reg1 reg2 ep bit#3 immx dispx regID vector cccc Description General-purpose register (r0 to r31): Used as source register General-purpose register (r0 to r31): Mainly used as destination register Element pointer (r30) 3-bit data for bit number specification x-bit immediate data x-bit displacement System register number 5-bit data that specifies trap vector number (00H to 1FH) 4-bit data that indicates condition code 574 User's Manual U14665EJ4V0UD APPENDIX C INSTRUCTION SET LIST Table C-2. Symbols Used for Opcode Symbol R r d i cccc bbb Description 1-bit data of code that specifies reg1 or regID 1-bit data of code that specifies reg2 1-bit data of displacement 1-bit data of immediate data 4-bit data that indicates condition code 3-bit data that specifies bit number Table C-3. Symbols Used for Operation Description Symbol GR[ ] SR[ ] zero-extend (n) sign-extend (n) load-memory (a,b) store-memory (a,b,c) load-memory-bit (a,b) store-memory-bit (a,b,c) saturated (n) Assignment General-purpose register System register Zero-extends n to word length. Sign-extends n to word length. Reads data of size b from address a. Writes data b of size c to address a. Reads bit b from address a. Writes c to bit b of address a Performs saturated processing of n. (n is 2's complement). Result of calculation of n: If n is n 7FFFFFFFH as result of calculation, 7FFFFFFFH. If n is n 80000000H as result of calculation, 80000000H. result Byte Halfword Word + - || x / AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflects result to a flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Add Subtract Bit concatenation Multiply Divide Logical product Logical sum Exclusive logical sum Logical negate Logical left shift Logical right shift Arithmetic right shift User's Manual U14665EJ4V0UD Description 575 APPENDIX C INSTRUCTION SET LIST Table C-4. Symbols Used for Flag Operation Symbol (blank) 0 x R Not affected Cleared to 0 Set of cleared according to result Previously saved value is restored Description Table C-5. Condition Codes Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 Conditional Expression OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) NC/NL 1001 CY = 0 No carry No lower (Greater than or equal) Z/E 0010 Z=1 Zero Equal NZ/NE 1010 Z=0 Not zero Not equal NH H N P T SA LT GE LE GT 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S XOR OV) = 1 (S XOR OV) = 0 ( (S XOR OV) OR Z) = 1 ( (S XOR OV) OR Z) = 0 (CY OR Z) = 1 (CY OR Z) = 0 S=1 S=0 - Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Description 576 User's Manual U14665EJ4V0UD APPENDIX C INSTRUCTION SET LIST Instruction Set List (1/4) Instruction Group Load/store Mnemonic Operand Opcode Operation CY OV SLD.B disp7 [ep], reg2 rrrrr0110ddddddd adr ep + zero-extend (disp7) GR [reg2] sign-extend (Load-memory (adr, Byte)) SLD.H disp8 [ep], reg2 rrrrr1000ddddddd adr ep + zero-extend (disp8) (adr, Halfword)) SLD.W disp8 [ep], reg2 LD.B disp16 rrrrr1010dddddd0 adr ep + zero-extend (disp8) adr GR [reg1] + sign-extend (disp16) GR [reg2] sign-extend (Load-memory (adr, Byte)) LD.H disp16 rrrrr111001RRRRR adr GR [reg1] + sign-extend (disp16) Flag S Z SAT Note 1 GR [reg2] sign-extend (Load-memory Note 2 GR [reg2] Load-memory (adr, Word) rrrrr111000RRRRR [reg1], reg2 dddddddddddddddd [reg1], reg2 ddddddddddddddd0 GR [reg2] sign-extend (Load-memory Note 3 (adr, Halfword)) adr GR [reg1] + sign-extend (disp16) GR [reg2] Load-memory (adr, Word)) adr ep + zero-extend (disp7) Store-memory (adr, GR [reg2], Byte) adr ep + zero-extend (disp8) adr ep + zero-extend (disp8) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Byte) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Halfword) adr GR [reg1] + sign-extend (disp16) Store-memory (adr, GR [reg2], Word) GR [reg2] GR [reg1] GR [reg2] sign-extend (imm5) GR [reg2] GR [reg1] + (imm16 || 0 ) 16 LD.W disp16 rrrrr111001RRRRR Note 3 [reg1], reg2 ddddddddddddddd1 SST.B reg2, disp7 [ep] rrrrr0111ddddddd SST.H reg2, disp8 [ep] rrrrr1001ddddddd Note 1 Store-memory (adr, GR [reg2], Halfword) rrrrr1010dddddd1 SST.W reg2, disp8 [ep] Note 2 Store-memory (adr, GR [reg2], Word) rrrrr111010RRRRR dddddddddddddddd ST.B reg2, disp16 [reg1] ST.H reg2, disp16 [reg1] rrrrr111011RRRRR ddddddddddddddd0 Note 3 rrrrr111011RRRRR ddddddddddddddd1 Note 3 rrrrr000000RRRRR ST.W reg2, disp16 [reg1] Arithmetic operation MOV MOV MOVHI reg1, reg2 imm5, reg2 rrrrr010000iiiii imm16, reg1, reg2 rrrrr110010RRRRR iiiiiiiiiiiiiiii rrrrr110001RRRRR iiiiiiiiiiiiiiii MOVEA imm16, reg1, reg2 GR [reg2] GR [reg1] + sign-extend (imm16) Notes 1. 2. 3. ddddddd is the higher 7 bits of disp8. dddddd is the higher 6 bits of disp8. ddddddddddddddd is the higher 15 bits of disp16. User's Manual U14665EJ4V0UD 577 APPENDIX C INSTRUCTION SET LIST Instruction Set List (2/4) Instruction Group Arithmetic operation Mnemonic Operand Opcode Operation CY OV ADD ADD reg1, reg2 imm5, reg2 rrrrr001110RRRRR rrrrr010010iiiii GR [reg2] GR [reg2] + GR [reg1] GR [reg2] GR [reg2] + sign-extend (imm5) ADDI imm16, reg1, reg2 SUB SUBR MULH reg1, reg2 reg1, reg2 reg1,reg2 rrrrr110000RRRRR iiiiiiiiiiiiiiii rrrrr001101RRRRR rrrrr001100RRRRR rrrrr000111RRRRR GR [reg2] GR [reg1] + sign-extend (imm16) GR [reg2] GR [reg2] - GR [reg1] GR [reg2] GR [reg1] - GR [reg2] GR [reg2] GR [reg2] Note Flag S x x x x x Z SAT x x x x x x x x x x Note x x x x x x GR [reg1] (Signed multiplication) MULH imm5, reg2 rrrrr010111iiiii GR [reg2] GR [reg2] (imm5) MULHI imm16, reg1, reg2 DIVH reg1, reg2 rrrrr110111RRRRR iiiiiiiiiiiiiiii rrrrr000010RRRRR Note x sign-extend x imm16 Note (Signed multiplication) Note GR [reg2] GR [reg1] (Signed multiplication) GR [reg2] GR [reg2] / GR [reg1] result GR [reg2] - GR [reg1] result GR [reg2] - sign-extend (imm5) if conditions are satisfied then GR [reg2] 00000001H else GR [reg2] 00000000H GR [reg2] saturated (GR [reg2] + GR [reg1]) GR [reg2] saturated (GR [reg2] + signextend (imm5)) GR [reg2] saturated (GR [reg2] - GR [reg1]) GR [reg2] saturated (GR [reg1] - signextend (imm16)) GR [reg2] saturated (GR [reg1] - GR [reg2]) result GR [reg2] AND GR [reg1] GR [reg2] GR [reg2] OR GR [reg1] GR [reg2] GR [reg1] OR zero-extend (imm16) GR [reg2] GR [reg2] AND GR [reg1] GR [reg2] GR [reg1] AND zero-extend (imm16) 0 0 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x (Signed division) CMP CMP SETF reg1, reg2 imm5, reg2 cccc, reg2 rrrrr001111RRRRR rrrrr010011iiiii rrrrr1111110cccc 0000000000000000 Saturated operation SATADD reg1, reg2 rrrrr000110RRRRR SATADD imm5, reg2 rrrrr010001iiiii SATSUB reg1, reg2 rrrrr000101RRRRR SATSUBI imm16, reg1, reg2 rrrrr110011RRRRR iiiiiiiiiiiiiiii rrrrr000100RRRRR SATSUBR reg1, reg2 Logic operation TST OR ORI reg1, reg2 reg1, reg2 imm16, reg1, reg2 rrrrr001011RRRRR rrrrr001000RRRRR rrrrr110100RRRRR iiiiiiiiiiiiiiii rrrrr001010RRRRR rrrrr110110RRRRR iiiiiiiiiiiiiiii 0 0 0 AND ANDI reg1, reg2 imm16, reg1, reg2 Note Only the lower halfword data is valid. 578 User's Manual U14665EJ4V0UD APPENDIX C INSTRUCTION SET LIST Instruction Set List (3/4) Instruction Group Logic operation Operand Opcode Flag Operation CY OV XOR XORI reg1, reg2 imm16, reg1, reg2 NOT SHL reg1, reg2 reg1, reg2 rrrrr001001RRRRR rrrrr110101RRRRR iiiiiiiiiiiiiiii rrrrr000001RRRRR rrrrr111111RRRRR 0000000011000000 SHL imm5, reg2 rrrrr010110iiiii GR [reg2] GR [reg2] XOR GR [reg1] GR [reg2] GR [reg1] XOR zero-extend (imm16) GR [reg2] NOT (GR [reg1]) GR [reg2] GR [reg2] logically shift left by GR [reg1]) GR [reg2] GR [reg2] logically shift left by zero-extend (imm5) SHR reg1, reg2 rrrrr1111111cccc 0000000010000000 SHR imm5, reg2 rrrrr010100iiiii GR [reg2] GR [reg2] logically shift right by GR [reg1] GR [reg2] GR [reg2] logically shift right by zero-extend (imm5) SAR reg1, reg2 rrrrr111111RRRRR 0000000010100000 SAR imm5, reg2 rrrrr010101iiiii GR [reg2] GR [reg2] arithmetically shift right by GR [reg1] GR [reg2] GR [reg2] arithmetically shift right by zero-extend (imm5) Jump JMP [reg1] 00000000011RRRR R JR disp22 0000011110dddddd ddddddddddddddd0 Note 1 JARL disp22, reg2 Bcond disp9 rrrrr11110dddddd ddddddddddddddd0 Note 1 ddddd1011dddcccc if conditions are satisfied Note 2 then PC PC + sign-extend (disp9) x GR [reg2] PC + 4 PC PC + sign-extend (disp22) PC PC + sign-extend (disp22) PC GR [reg1] x 0 x x x 0 x x x 0 x x x 0 x x x 0 x x x 0 0 x x x x 0 0 S x x Z SAT x x Mnemonic Bit manipulate SET1 bit#3, disp16 [reg1] 00bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3) Store memory-bit (adr, bit#3, 1) CLR1 bit#3, disp16 [reg1] 10bbb111110RRRR R dddddddddddddddd adr GR [reg1] + sign-extend (disp16) Z flag Not (Load-memory-bit (adr, bit#3)) Store memory-bit (adr, bit#3, 0) x NOT1 bit#3, disp16 [reg1] 01bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag) x TST1 bit#3, disp16 [reg1] 11bbb111110RRRRR adr GR [reg1] + sign-extend (disp16) dddddddddddddddd Z flag Not (Load-memory-bit (adr, bit#3)) x Notes 1. 2. ddddddddddddddddddddd is the higher 21 bits of dip22. dddddddd is the higher 8 bits of disp9. User's Manual U14665EJ4V0UD 579 APPENDIX C INSTRUCTION SET LIST Instruction Set List (4/4) Instruction Group Special Mnemonic Operand Opcode SR [regID] GR [reg2] Flag Operation CY OV S LDSR reg2, regID rrrrr111111RRRRR 0000000000100000 Note regID = EIPC, FEPC regID = EIPSW, FEPSW regID = PSW STSR regID, reg2 rrrrr111111RRRRR 0000000001000000 TRAP vector 00000111111iiiii 0000000100000000 EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC + 4 (Restored PC) PSW Interrupt code 1 1 GR [reg2] SR [regID] x x x x x Z SAT PC 00000040H (vector = 00H to 0FH) 00000050H (vector = 10H to 1FH) RETI 0000011111100000 0000000101000000 if PSW.EP = 1 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW HALT 0000011111100000 0000000100100000 DI 0000011111100000 0000000101100000 EI 1000011111100000 0000000101100000 NOP 0000000000000000 PSW.ID 1 (Maskable interrupt disabled) PSW.ID 0 (Maskable interrupt enabled) Uses 1 clock cycle without doing anything Stops R R R R R Note The opcode of this instruction uses the field of reg1 even though the source register is shown as reg2 in the above table. Therefore, the meaning of register specification for mnemonic description and opcode is different from that of the other instructions. rrrrr = regID specification RRRRR = reg2 specification 580 User's Manual U14665EJ4V0UD APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition Page Throughout Addition of following special grade products Description PD703075AY(A), 703076AY(A), 703078AY(A), 703079AY(A), 70F3079AY(A) p. 50 p. 128 Addition of operation description of FEPC and FEPSW registers in Table 3-2 System Register Numbers Modification of P114 to P117 and addition of Note 1 in Table 5-12 Setting When Port Pin Is Used for Alternate Function p. 231 p. 233 p. 246 p. 322 p. 365 p. 401 p. 530 Addition of Remark in Figure 8-34 Square-Wave Output Operation Timing Addition of Remark in Figure 8-35 Timing of PWM Output Modification of description in 10.4.1 Operation as watchdog timer Addition of Caution 3 in Figure 11-26 ASIMn Setting (Asynchronous Serial Interface Mode) Addition of 12.7 How to Read A/D Converter Characteristics Table Addition of Caution in 17.5.6 Power supply Addition of <9> in 18.16 Cautions on Use D.2 Revision History up to Preceding Edition The following table shows the revision history up to the previous editions. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/7) Edition 2nd Major Revision from Previous Edition Modification of regulator voltage Modification of 1.4 Ordering Information Applied to: Throughout CHAPTER 1 INTRODUCTION Modification of description in 2.3 (5) P40 to P47 (port 4) Modification of description in 2.3 (6) P50 to P57 (port 5) Modification of description in 2.3 (7) P60 to P65 (port 6) Modification of description in 2.3 (9) P90 to P96 (port 9) Addition of 2.3 (18) CLKOUT (Clock Out) Modification of Figure 3-12 Application of Wraparound CHAPTER 3 CPU FUNCTIONS Addition of Caution to 4.4.4 (1) Settings and operating states Addition of 4.6 Cautions on Power Save Function Modification of 5.2.4 (1) Function of P3 pins Modification of Figure 5-12 Block Diagram of P110 and P114 to P117 Addition of 7.8 (1) Acknowledgement of interrupt servicing following EI instruction CHAPTER 4 CLOCK GENERATION FUNCTION CHAPTER 5 PORT FUNCTION CHAPTER 7 INTERRUPT/EXCEP TION PROCESSING FUNCTION CHAPTER 2 PIN FUNCTIONS User's Manual U14665EJ4V0UD 581 APPENDIX D REVISION HISTORY (2/7) Edition 2nd Major Revision from Previous Edition Modification of Caution in 8.1.3 (2) Capture/compare register n0 (CR00, CR10, CR70) Modification of Caution in 8.1.3 (3) Capture/compare register n1 (CR01, CR11, CR71) Modification of Caution in Figure 8-21 Control Register Settings for One-Shot Pulse Output with Software Trigger Modification of Caution in Figure 8-23 Control Register Settings for One-Shot Pulse Output with External Trigger Modification of Figure 8-27 Data Hold Timing of Capture Register Addition of 8.2.7 (6) (c) One-shot pulse output function Modification of Caution in 9.3 (2) Watch timer clock selection register (WTNCS) CHAPTER 9 WATCH TIMER FUNCTION Addition of Remark to 11.2.2 (1) Serial operation mode register n (CSIMn) Addition of Remark to Figure 11-3 CSIMn Setting (3-Wire Serial I/O Mode) Addition of 11.3.2 (6) I C0 transfer clock setting method Modification of Table 11-3 Selection Clock Setting Addition of Remark to 11.4.2 (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) Addition of Remark to Figure 11-29 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) Modification of 12.3 (1) A/D converter mode register 1 (ADM1) Addition of description to 12.5 Low Power Consumption Mode Modification of Figure 15-1 Regulator CHAPTER 12 A/D CONVERTER CHAPTER 15 REGULATOR Addition of Caution to 16.1 General Deletion of Caution from 16.2.1 Correction control register (CORCN) Addition of Caution to CHAPTER 17 FLASH MEMORY (PD70F3079Y) CHAPTER 16 ROM CORRECTION FUNCTION CHAPTER 17 FLASH MEMORY (PD70F3079Y) Modification of description in Table 18-1 Overview of Functions Modification of Figure 18-1 Block Diagram of FCAN Modification of figure in 18.4.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) Modification of bit names in 18.4.2 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) Modification of description in 18.4.5 CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) Modification of figure in 18.4.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) Addition of Caution to 18.4.12 CAN stop register (CSTOP) Modification of GOM bit description in 18.4.13 CAN global status register (CGST) Modification of Figure 18-2 FCAN Clocks Modification of description of MFND4 to MFND0 bits in 18.4.17 CAN message search start/result register (CGMSS/CGMSR) CHAPTER 18 FCAN CONTROLLER 2 Applied to: CHAPTER 8 TIMER/COUNTER FUNCTION CHAPTER 11 SERIAL INTERFACE FUNCTION 582 User's Manual U14665EJ4V0UD APPENDIX D REVISION HISTORY (3/7) Edition 2nd Major Revision from Previous Edition Addition of Caution to 18.4.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) Modification of bit names in 18.4.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) Modification of bit names in 18.4.25 CANn bit rate prescaler register (CnBRP) Modification of Caution in 18.4.27 CANn synchronization control register (CnSYNC) Modification of 18.6 Time Stamp Function Modification of description in 18.7 Message Processing Modification of 18.8 <2> Identifier bits set to message buffer 14 (example) Modification of 18.8 <3> Mask setting for CAN module 1 (mask 1) (example) Modification of description in 18.10.7 (1) Prescaler Modification of 18.10.7 (2) Nominal bit time (8 to 25 time quantum) Modification of Figure 18-28 Setting of CAN Global Interrupt Enable Register (CGIE) Modification of Figure 18-30 Setting of CANn Bit Rate Prescaler Register (CnBRP) Modification of 18.11.3 Receive setting Modification of Figure 18-41 CAN Sleep Mode Setting Modification of Figure 18-44 CAN Stop Mode Setting Modification of Figure 18-45 Clearing of CAN Stop Mode Modification of 18.12 Rules for Correct Setting of Baud Rate Modification of 18.14.2 Burst read mode Modification of 18.15.2 Interrupts that occur for global CAN interface Addition of 18.17 Cautions on Use 3rd * Addition of the following products Applied to: CHAPTER 18 FCAN CONTROLLER Throughout PD703075AY, 703076AY, 703078AY, 703079AY, 70F3079AY * Deletion of indication "under development" for the following products (developed) PD703078YGF-xxx-3BA, 703079YGF-xxx-3BA, 70F3079YGF-3BA Addition of description on internal memory in 1.2 Features CHAPTER 1 INTRODUCTION Modification of description in Table 2-1 Pin I/O Buffer Power Supplies Modification of description and addition of Notes in Table 2-2 Pin Operating State According to Operation Mode Modification of description in 2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins Addition of 3.4.5 (1) (a) <1> PD703075AY, 703076AY Addition of 3.4.5 (2) (a) PD703075AY, 703076AY Modification of description and addition of Notes in 3.4.8 Peripheral I/O registers Modification of description in 3.4.9 Specific registers Addition of Remarks in 3.4.9 (2) System status register (SYS) Addition to Notes and Cautions in 4.3.1 (1) Processor clock control register (PCC) Modification of description for setting DCLK1 and DCLK0 bits = 01 and addition to Notes in 4.3.1 (2) Power save control register (PSC) CHAPTER 4 CLOCK GENERATION FUNCTION CHAPTER 3 CPU FUNCTIONS CHAPTER 2 PIN FUNCTIONS User's Manual U14665EJ4V0UD 583 APPENDIX D REVISION HISTORY (4/7) Edition 3rd Major Revision from Previous Edition Addition of Note on the value after reset in 4.3.1 (3) Oscillation stabilization time selection register (OSTS) Modification of description on operation status of A16 to A21 pins in Table 4-1 Operating Statuses in HALT Mode Modification of description on operation of UART0 and UART1 in Table 4-2 Operating Statuses in IDLE Mode Addition of description in 4.4.4 (1) Settings and operating states Modification of description on operation status of UART0 and UART1 in Table 4-3 Operating Statuses in Software STOP Mode Addition of description in 4.5 (2) Use of RESET pin to secure time (RESET pin input) Addition of 4.6 (1) When executing an instruction on internal ROM Addition of Caution in 4.6 (2) When executing an instruction on external ROM Modification of description in Table 5-1 Pin I/O Buffer Power Supplies Modification of description in 5.2.4 (2) (a) Port 3 mode register (PM3) Addition and modification of description in Table 5-12 Setting When Port Pin Is Used for Alternate Function Addition of 5.4 Operation of Port Function Addition of description and modification in Table 7-1 Interrupt Source List Modification of description in Figure 7-2 Acknowledging Non-Maskable Interrupt Requests Addition of Caution in 7.3.5 In-service priority register (ISPR) Addition of 7.8.1 Interrupt request valid timing following EI instruction Addition of 7.9 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer Addition and modification of description in 8.1.3 (2) Capture/compare register n0 (CR00, CR10, CR70) Addition and modification of description in 8.1.3 (3) Capture/compare register n1 (CR01, CR11, CR71) Addition to Cautions in 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 (TMC0, TMC1, TMC7) Addition to Cautions in 8.1.4 (2) Capture/compare control registers 0, 1, 7 (CRC0, CRC1, CRC7) Addition of Figure 8-6 Configuration of PPG Output and Figure 8-7 PPG Output Operation Timing Change of description of Caution in 8.2.6 (2) One-shot pulse output with external trigger Addition of Caution in 8.3.2 (2) 16-bit compare registers 2 to 6 (CR2 to CR6) Addition of (3) in 8.4.5 Cautions Modification of description and addition of Note in 10.3 (1) Oscillation stabilization time selection register (OSTS) Addition of Caution in 10.3 (2) Watchdog timer clock selection register (WDCS) Modification of description and addition of Note in 10.5 Standby Function Control Register Addition of description in 11.2 (2) 3-wire serial I/O mode (fixed to MSB first) Addition to Cautions in 11.2.2 (1) Serial operation mode register n (CSIMn) CHAPTER 11 SERIAL INTERFACE FUNCTION CHAPTER 10 WATCHDOG TIMER FUNCTION CHAPTER 8 TIMER/COUNTER FUNCTION CHAPTER 7 INTERRUPT/ EXCEPTION PROCESSING FUNCTION CHAPTER 5 PORT FUNCTION Applied to: CHAPTER 4 CLOCK GENERATION FUNCTION 584 User's Manual U14665EJ4V0UD APPENDIX D REVISION HISTORY (5/7) Edition 3rd Major Revision from Previous Edition Modification of description and addition of Caution in 11.3.2 (3) IIC clock expansion register 0 (IICCE0), IIC function expansion register 0 (IICX0), IIC clock selection register 0 (IICCL0) Addition to Cautions in 11.4.2 (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) Addition to Cautions in 11.4.2 (4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1) Addition to Cautions in Figure 11-25 ASIMn Setting (Operation Stopped Mode) Addition to Cautions in Figure 11-26 ASIMn Setting (Asynchronous Serial Interface Mode) Addition to Cautions in Figure 11-29 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode) Modification of Caution in 12.2 (2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Modification and addition of description in 12.3 (1) A/D converter mode register 1 (ADM1) Addition of Caution in 12.3 (2) Analog input channel specification register (ADS) Addition of Figure 12-3 A/D Conversion by Software Start/Hardware Start (When ADPS Bit = 0) Addition of Figure 12-4 A/D Conversion by Software Start/Hardware Start (When ADPS Bit = 1) Modification of description in 12.6 (3) <3> Conflict between writing of ADCR and writing A/D converter mode register 1 (ADM1) or analog input channel specification register (ADS) Modification of description in 12.6 (8) Reading A/D converter result register (ADCR) Addition of 13.3 Configuration Addition of Table 13-1 Internal RAM Area Usable for DMA Addition of 13.4 (2) (a) PD703075AY, 703076AY Addition to Cautions in 13.4 (6) Trigger settings Addition of 13.5 Operation Addition of 13.6 Cautions Addition of 14.1 (2) Internal reset by power-on-clear (POC) Addition of Note in Figure 14-1 Timing of Rest by RESET Input Addition of Figure 14-2 Timing of Reset by Power-on-Clear Addition of Note in 16.2.2 Correction request register (CORRQ) Modification of description in 16.2.3 Correction address registers 0 to 3 (CORAD0 to CORAD3) Addition of Figure 17-1 Example of Wiring of Adapter for Flash Programming (FA100GC-8EU) Addition of Table 17-1 Table for Wiring of Adapter for PD70F3079AY and 70F30789Y Flash Programming (FA-100GC-8EU) Modification of description and Note in Table 17-2 Signal Generation of Dedicated Flash Programmer (PG-FP3) Modification and addition of description in Table 17-5 Flash Memory Control Commands User's Manual U14665EJ4V0UD Applied to: CHAPTER 11 SERIAL INTERFACE FUNCTION CHAPTER 12 A/D CONVERTER CHAPTER 13 DMA FUNCTIONS CHAPTER 14 RESET FUNCTION CHAPTER 16 ROM CORRECTION FUNCTION CHAPTER 17 FLASH MEMORY (PD70F3079AY AND 70F3079Y) 585 APPENDIX D REVISION HISTORY (6/7) Edition 3rd Major Revision from Previous Edition Change of manipulatable bits and reset values in 18.3.2 List of FCAN registers Modification of description and addition of Note and Caution in 18.4.1 CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) Modification of description and addition of Note in 18.4.2 CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) Addition of description in 18.4.6 CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) Modification of description in 18.4.7 CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) Modification of description on manipulatable bits and modification of register format in 18.4.10 CAN global interrupt pending register (CGINTP) Modification of description on manipulatable bits and modification of register format in 18.4.11 CANn interrupt pending register (CnINTP) Addition to Cautions in 18.4.12 CAN stop register (CSTOP) Modification of description on manipulatable bits and modification of bit description in 18.4.13 CAN global status register (CGST) Modification of description on manipulatable bits in 18.4.14 CAN global interrupt enable register (CGIE) Addition of description and Caution in 18.4.15 CAN main clock selection register (CGCS) Addition of Cautions in 18.4.17 CAN message search start/result register (CGMSS/CGMSR) Addition of description in 18.4.18 CANn address mask a registers L and H (CnMASKLa and CnMASKHa) Modification and addition of bit description in 18.4.19 CANn control register (CnCTRL) Addition of 18.4.19 (1) TMR bit setting Modification of description on manipulatable bits and modification of bit description in 18.4.20 CANn definition register (CnDEF) Modification of description on manipulatable bits and addition of bit description in 18.4.23 CANn interrupt enable register (CnIE) Modification of description in Cautions and addition of bit description in 18.4.27 CANn synchronization control register (CnSYNC) Addition of Cautions in 18.6 Time Stamp Function Modification of description in 18.7 Message Processing Addition to Note in Figure 18-24 Nominal Bit Time Addition of description in 18.10.7 (3) (b) Resynchronization Addition of description in Figure 18-27 Initialization Processing Addition of Note in Figure 18-32 Setting of CANn Synchronization Control Register (CnSYNC) Addition of description in Figure 18-37 Message Buffer Setting Addition of Figure 18-40 Setting of CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Addition of Figure 18-42 Setting of Receive Completion Interrupt and Receive Operation Using Reception Polling Applied to: CHAPTER 18 FCAN CONTROLLER 586 User's Manual U14665EJ4V0UD APPENDIX D REVISION HISTORY (7/7) Edition 3rd Major Revision from Previous Edition Addition of Figure 18-43 Setting of CAN Message Search Start/Result Register (CGMSS/CGMSR) Addition of description in Figure 18-47 CAN Stop Mode Setting Addition of description in Figure 18-48 Clearing of CAN Stop Mode Modification of description in 18.12 Rules for Correct Setting of Baud Rate Modification of description in Figure 18-50 Sequential Data Read Addition to Cautions in 18.13.2 Burst read mode Deletion of Caution 2 in 18.15 How to Shut Down FCAN Controller Addition of <4> to <8> in 18.16 Cautions on Use Addition of CHAPTER 19 ELECTRICAL SPECIFICATIONS CHAPTER 19 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 20 PACKAGE DRAWINGS CHAPTER 20 PACKAGE DRAWINGS Addition of CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN APPENDIX A NOTES ON TARGET SYSTEM DESIGN Addition of APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY Applied to: CHAPTER 18 FCAN CONTROLLER User's Manual U14665EJ4V0UD 587 |
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